Method and structure for metal-insulator-metal capacitor based memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorKuo-Chi Tu
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Abstract
A process for integrally fabricating a memory cell capacitor and a logic device is disclosed. A first conductive layer and second conductive layer are formed above a semiconductor substrate with a logic region and memory cell region. A first photoresist layer is formed to cover the logic region, and expose an inter-metal dielectric layer adjacent to the second conductive layer in the memory cell region. The exposed inter-metal dielectric layer is etched off to form an opening adjacent to the second conductive layer. A capacitor dielectric layer and third conductive layer are formed on inner walls of the opening to constitute a metal-insulator-metal capacitor.
Claims25
A method for integrally fabricating a memory cell capacitor and a logic device, the method comprising:
- providing a semiconductor substrate having a logic region and a memory cell region;
- forming a first conductive layer in the logic region and a second conductive layer in the memory cell region, above the semiconductor substrate;
- forming a first photoresist layer covering the logic region, and exposing the second conductive layer and a neighboring part of an inter-metal dielectric layer adjacent to the second conductive layer;
- etching off the exposed neighboring part of the inter-metal dielectric layer to form an opening adjacent to the second conductive layer;
- forming a capacitor dielectric layer on inner walls of the opening;
- and
- forming a third conductive layer on the capacitor dielectric layer in the opening wherein the third conductive layer, the capacitor dielectric layer and the second conductive layer constitute a capacitor.
A semiconductor capacitor structure comprising:
- a substrate having an active area;
- a first capacitor electrode having a first conductive layer above the active area and connected to the same, and a second conductive layer formed above the first conductive layer, wherein the second conductive layer is electrically coupled to the first conductive layer;
- a capacitor dielectric layer formed on a side wall of the second conductive layer;
- and
- a second capacitor electrode formed on the capacitor dielectric layer and extending beyond the vertical boundary of the first conductive layer, whereby an aspect ratio during forming the first capacitor electrode is improved.
A semiconductor device comprising:
- a logic device disposed on a substrate;
- a memory cell, having at least one transistor device, disposed on the substrate, the memory cell comprising:
- a first capacitor electrode having a first conductive layer connected to the transistor device, and a second conductive layer formed above the first conductive layer, and electrically coupled to the same;
- a capacitor dielectric layer formed on a side wall of the second conductive layer;
- and
- a second capacitor electrode formed on the capacitor dielectric layer and extending beyond the vertical boundary of the first conductive layer, whereby an aspect ratio during forming the first capacitor electrode is improved.
Dependencies are inferred from the claim text.