Integrated high voltage capacitor having a top-level dielectric layer and a method of manufacture therefor

A method for manufacturing an integrated high voltage capacitor, comprising:

• forming a first capacitor plate over or in a substrate;
• forming an insulator over the first capacitor plate, at least a portion of the insulator comprising an interlevel dielectric layer;
• forming a second capacitor plate over the insulator;
• and
• forming a top-level dielectric layer at least partially along a sidewall of the second capacitor plate.

An integrated circuit chip, comprising:

• one or more transistors located over or in a substrate, the one or more transistor having one or more interlevel dielectric layers located thereover;
• a high voltage capacitor including a first capacitor plate, an insulator and a second capacitor plate located at least partially in or over the substrate, wherein at least one of the one or more interlevel dielectric layers forms at least a portion of the insulator;
• and
• a top-level dielectric layer located at least partially along a sidewall of the second capacitor plate, the top-level dielectric layer configured to reduce parasitic leakage between the second capacitor plate and other conductive features located proximate thereto.