# US 2006/0189061 A1 · CMOS silicide metal gate integration

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- Number: US 2006/0189061 A1
- Document ID: US20060189061A1
- Status: Published application
- Kind: A1
- Application number: 11/407,313
- Filed: 2006-04-19
- Published: 2006-08-24
- Earliest claimed: 2004-02-25
- Assignees: International Business Machines Corporation
- Inventors: Ricky Amos; Diane Boyd; Cyril Cabral; Richard Kaplan; Jakub Kedzierski; Victor Ku; Woo-Hyeong Lee; Ying Li; Anda Mocuta; Vijay Narayanan; An Steegen; Maheswaren Surendra
- Web page: https://patentgrep.com/patent/US20060189061A1

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/0132: {the conductor being a metallic silicide}
- H10D 84/0174: {the gate conductors being silicided}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

## Claims

### Claim 1

A CMOS structure comprising;
a plurality of silicided metal gates located atop a surface of a gate dielectric, each of the silicided metal gates is composed of the same silicide phase, has substantially the same height, and has substantially the same workfunction for the same polySi ion implant conditions regardless of the dimension of the silicided metal gate.

### Claim 2 (depends on 1)

The CMOS structure of claim 1 wherein the silicided metal gates comprise a metal selected from the group consisting of Ti, Ta, W, Co, Ni, Pt, Pd and alloys thereof.

### Claim 3 (depends on 2)

The CMOS structure of claim 2 wherein the metal is Co, Ni or Pt.

### Claim 4 (depends on 1)

The CMOS structure of claim 1 further comprising a gate dielectric located between each silicided metal gate and the semiconductor substrate.

### Claim 5 (depends on 4)

The CMOS structure of claim 4 wherein the gate dielectric comprises SiO2, SiOxNy, HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, SrTiO3, LaAlO3, silicates or combinations thereof.

### Claim 6 (depends on 1)

The CMOS structure of claim 1 further comprising silicided source/drain regions adjoining each silicided metal gate.

### Claim 7 (depends on 1)

The CMOS structure of claim 1 wherein each silicided metal gate comprises CoSi2, PtSi or NiSi.

### Claim 8 (depends on 1)

The CMOS structure of claim 1 wherein at least one spacer is located on sidewalls of each of the silicided metal gates.

### Claim 9 (depends on 8)

The CMOS structure of claim 8 wherein the at least one spacer includes a first narrow spacer and a second wider spacer.

### Claim 10 (depends on 1)

The CMOS structure of claim 1 wherein the silicide gates include a dopant selected from the group consisting of As, P, B, Sb, Bi, In, Al, Ga, Tl and mixtures thereof, the dopant changes the workfunction of the silicided metal gate.

### Claim 11

A method of forming a CMOS structure having silicide contacts comprising the step of:
providing a structure comprising a plurality of polySi gates overlying a semiconductor substrate;
depositing a silicide metal atop the structure including the polySi gates and the semiconductor substrate;
forming a recessed, reflow material between each polySi gate;
removing silicide metal from atop each of the polySi gates;
removing the recessed, reflow material; and
annealing the structure so as to form silicide contact regions between each of the polySi gates.

### Claim 12 (depends on 11)

The method of claim 11 wherein the silicide metal comprises Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof.

### Claim 13 (depends on 12)

The method of claim 12 wherein the metal is Co, Ni or Pt.

### Claim 14 (depends on 11)

The method of claim 11 wherein the recessed, reflow material comprises an antireflective coating or a spin-on dielectric.

### Claim 15 (depends on 11)

The method of claim 11 wherein the forming the recessed, reflow material comprises deposition and optional etching.

### Claim 16 (depends on 11)

The method of claim 11 wherein the removing the silicide metal comprises a wet etching process.

### Claim 17 (depends on 11)

The method of claim 11 wherein the annealing includes at least a first annealing step which is performed at a temperature from about 300° C. to about 600° C.

### Claim 18 (depends on 17)

The method of claim 17 further comprising an optional second annealing step which is performed at a temperature from about 600° C. to about 800° C.

### Claim 19 (depends on 11)

The method of claim 11 further comprising forming silicide metal gates by depositing and planarizing a capping bilayer comprising SiO2 and Si3N4; performing an optional wet etch process to remove SiO2; performing a selective RIE process to remove Si3N4 atop the gate; forming a silicide metal on the gate; and performing a salicide process.

### Claim 20

A method of forming a CMOS structure having silicide contacts comprising the step of:
providing a structure comprising a plurality of polySi gates overlying a semiconductor substrate;
forming a bilayer layer comprising a metal-containing layer and a capping layer atop the structure including the polySi gates and the semiconductor substrate;
forming a planarizing material on the semiconductor substrate;
exposing the metal-containing layer atop each polySi gate;
removing the metal-containing layer from atop each polySi gate;
planarizing the planarizing material; and
annealing the structure so as to form silicide contact regions between each of the polySi gates.

### Claim 21 (depends on 20)

The method of claim 20 wherein the metal-containing layer comprises Ti, Ta, W, Co, Ni, Pt, Pd or alloys thereof.

### Claim 22 (depends on 21)

The method of claim 21 wherein the metal-containing layer is Co, Ni or Pt.

### Claim 23 (depends on 20)

The method of claim 20 wherein the capping layer comprises TiN, W or Ti.

### Claim 24 (depends on 20)

The method of claim 20 wherein the planarizing material comprises a photoresist or a low temperature oxide.

### Claim 25 (depends on 20)

The method of claim 20 wherein the exposing comprises chemical mechanical polishing of the planarizing material and etching of the capping layer.

### Claim 26 (depends on 20)

The method of claim 20 wherein the removing of the metal-containing silicide metal from atop each polySi gate includes a wet etching process.

### Claim 27 (depends on 20)

The method of claim 20 wherein the annealing includes at least a first annealing step which is performed at a temperature from about 300° C. to about 600° C.

### Claim 28 (depends on 27)

The method of claim 27 further comprising an optional second annealing step which is performed at a temperature from about 600° C. to about 800° C.

### Claim 29 (depends on 20)

The method of claim 20 comprising forming silicide metal gates by depositing and planarizing a capping bilayer comprising SiO2 and Si3N4; performing an optional wet etch process to remove SiO2; performing a selective RIE process to remove Si3N4 atop the gate; forming a silicide metal on the gate; and performing a salicide process.

### Claim 30

A CMOS structure comprising:
a plurality of polySi gates located atop a surface of a gate dielectric, each of the polySi gates has substantially the same height, regardless of the dimension of the polysilicon gates and silicided contacts located between each polySi gate.

### Claim 31 (depends on 30)

The CMOS structure of claim 30 wherein the polySi gates include a dopant selected from the group consisting of As, P, B, Sb, Bi, In, Al, Ga, Tl and mixtures thereof.

### Claim 32 (depends on 30)

The CMOS structure of claim 30 wherein the silicide contacts comprise NiSi, CoSi2 or PtSi.

### Claim 33 (depends on 30)

The CMOS structure of claim 30 wherein the silicide contacts are self-aligned with outer edges of a spacer that is located on a sidewall of each polySi gate.