Semiconductor memory device with high operating current and method of manufacturing the same

A semiconductor memory device comprising:

• a semiconductor substrate in which a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region are defined;
• a MOS transistor in each of the memory cell region and the peripheral circuit region, including a gate electrode with sidewall spacers, a source region, and a drain region;
• an etch stop layer on the semiconductor substrate where the MOS transistors are formed;
• and
• an interlayer insulating layer on the etch stop layer,
• wherein each of etch stop layer portions in the memory cell region and the PMOS region is thicker than an etch stop layer portion in the NMOS region.

A semiconductor memory device comprising:

• a semiconductor substrate in which a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region are-defined;
• a MOS transistor in each of the memory cell region and the peripheral circuit region, including a gate electrode with sidewall spacers, a source region, and a drain region;
• a first etch stop layer formed on the semiconductor substrate where the MOS transistors are formed;
• a second etch stop layer selectively formed on the NMOS region;
• an interlayer insulating layer formed on each of the first etch stop layer and the second etch stop layer;
• first contact pads formed in the interlayer insulating layer to expose the source and drain regions of transistors in the memory cell region;
• and
• second contact pads formed in the interlayer insulating layer to expose the source and drain regions of transistors in the NMOS region.

A method of manufacturing a semiconductor memory device, the method comprising:

• providing a semiconductor substrate in which a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region are defined;
• forming a gate electrode with sidewall spacers in the memory cell region and forming a gate electrode with sidewall spacers in each of the NMOS region and the PMOS region of the peripheral circuit region;
• forming source and drain regions on the semiconductor substrate at sides of the gate electrodes to form MOS transistors;
• forming a first etch stop layer on the semiconductor substrate where the MOS transistors are formed;
• and
• selectively forming a second etch stop layer on the PMOS region of the peripheral circuit region.

A semiconductor memory device comprising:

• a semiconductor substrate in which a memory cell region and a peripheral circuit region including an NMOS region and a PMOS region are defined;
• a MOS transistor on each of the memory cell region and the peripheral circuit region, including a gate electrode with sidewall spacers, a source region, and a drain region;
• an etch stop layer on the semiconductor substrate where the MOS transistors are formed;
• and
• an interlayer insulating layer on the etch stop layer,
• wherein each of etch stop layer portions in the memory cell region and the NMOS region is thicker than an etch stop layer portion on the PMOS region.