Four-transistor Schmitt trigger inverter
AssigneeSharp Laboratories of America, Inc.
InventorsThemistokles Afentakis, Apostolos Voutsas, Paul Schuele
Life of this patent
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Abstract
A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
Claims21
A method for forming a four-transistor Schmitt trigger inverter, the method comprising:
- forming a two-transistor variable threshold level inverter including:
- forming an NMOS dual-gate thin-film transistor (DG-TFT) with a top gate, a back gate, and source/drain (S/D) regions;
- forming a PMOS DG-TFT with a top gate, a back gate, and S/D regions;
- forming a NMOS TFT;
- forming a PMOS TFT;
- connecting an NMOS TFT gate to an NMOS DG-TFT first S/D region, a PMOS DG-TFT first S/D region, and a PMOS TFT gate;
- and,
- connecting an NMOS TFT first S/D region to the NMOS DG-TFT back gate, the PMOS DG-TFT back gate, and a PMOS TFT first S/D region.
A four-transistor Schmitt trigger inverter, the Schmitt trigger inverter comprising:
- a NMOS dual-gate thin-film transistor (DG-TFT) having a top gate, a back gate, and source/drain regions;
- a PMOS DG-TFT having a top gate, a back gate, and S/D regions;
- an NMOS TFT having a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region, and a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate;
- and,
- a PMOS TFT having a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
A method for introducing hysteresis into the operation of a complementary metal-oxide semiconductor (CMOS) inverter, the method comprising:
- providing a circuit consisting of an NMOS thin-film transistor (TFT) series-connected to a PMOS TFT, interposed between a supply voltage and reference voltage;
- in response to a high logic output, creating a first switch point for the NMOS and PMOS TFTs, higher in voltage than the reference voltage but lower than the supply voltage;
- and,
- in response to a low logic output, creating a second switch point for the NMOS and PMOS TFT, higher in voltage than the reference voltage but lower than the first switch voltage.
Dependencies are inferred from the claim text.