Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer

A method of fabricating a semiconductor device comprising:

• performing well formation and isolation processing in a semiconductor body;
• forming a gate dielectric layer on the semiconductor body;
• forming a conductive gate layer on the gate dielectric layer;
• patterning the gate dielectric layer and the conductive gate layer to form gate structures;
• forming offset spacers on lateral edges of the gate structures;
• forming extension regions in the semiconductor body in NMOS and PMOS regions;
• forming sidewall spacers adjacent the offset spacers;
• implanting p-type dopant(s) to form source/drain regions in the PMOS region;
• performing a first thermal process to activate the source/drain regions in the PMOS region and drive in the implanted p-type dopant(s);
• subsequent to performing the first thermal process, implanting n-type dopant(s) to form source/drain regions in the NMOS region;
• forming a capped poly layer over the device;
• and
• performing a second thermal process to induce tensile strain into channel regions of the NMOS region.

A method of fabricating a semiconductor device comprising:

• performing well formation and isolation processing in a semiconductor body;
• forming gate structures comprised of a gate dielectric layer and a conductive gate layer;
• implanting a first type dopant to form source/drain regions in a first region;
• performing a first thermal process to activate the source/drain regions in the first region and drive in the implanted first type dopant;
• subsequent to performing the first thermal process, forming a capped poly layer over the device;
• and
• performing a second thermal process to induce a type and amount of strain into channel regions within the first region, wherein the type and amount of strain is selected to improve channel mobility of devices within the first region.