Delay locked loop circuitry for clock delay adjustment

A delay locked loop circuit, comprising:

• a first loop circuit including a first adjustable delay section to provide a first clock signal having a controlled phase relationship with respect to an external clock signal;
• a first phase detector to receive the external clock signal and a first feedback clock signal, the first phase detector to provide a signal that is representative of a phase difference between the first feedback clock signal and the external clock signal;
• a first control circuit coupled to the first phase detector, the first control circuit to provide a plurality of control signals based on the signal that is representative of the phase difference between the first feedback clock signal and the external clock signal;
• and
• a selection block coupled to the first adjustable delay section, the selection block to adjust a phase of a second clock signal based on the plurality of control signals, wherein the second clock signal is used to generate the first feedback clock signal.

A method of operation in a delay locked loop circuit, the method comprising:

• generating a first clock signal in a first loop circuit such that the first clock signal includes a controlled phase relationship with respect to an external clock signal;
• and
• in a second loop circuit:
• comparing a phase of an external clock signal to a phase of a feedback clock signal to provide a signal that is representative of a phase difference between the feedback clock signal and the external clock signal;
• generating a plurality of control signals based on the signal that is representative of the phase difference between the feedback clock signal and the external clock signal;
• and
• adjusting a phase of a second clock signal based on the plurality of control signals, wherein the second clock signal is used to generate the feedback clock signal.

An integrated circuit memory device, comprising:

• a first loop circuit including a first adjustable delay section to provide a first clock signal having a controlled phase relationship with respect to an external clock signal;
• a second loop circuit including a selection block coupled to the first adjustable delay section, the selection block to adjust a phase of a second clock signal based on a phase difference between a first feedback clock signal and the external clock signal, wherein the second clock signal is used to generate the first feedback clock signal;
• and
• a transmitter circuit to output data on both edges of the second clock signal.