Clock Extracting Circuit

A clock extracting circuit for receiving an encoded signal into which a digital signal subject to transmission has been encoded based on a clock signal and for extracting the clock signal from the encoded signal, the clock extracting circuit comprising:

• an edge detector that detects rising edges and falling edges of the received encoded signal and produces edge detection pulses indicating the respective edges being detected;
• a mask signal generator that produces a mask signal which is inverted in phase in response to the edge detection pulses, which are produced one for each period of the received encoded signal, on the basis of the edge detection pulses one for the each period;
• a mask signal delay section that delays the mask signal by a delay time controllable and outputs the delayed mask signal;
• a clock generator that produces the clock signal on the basis of edges of the delayed mask signal;
• and
• a delay controller that controls the delay time of the mask signal delay section so as to set a duty ratio of the produced clock signal to a predetermined value.