Back to results
US 2006/0188043 A1Published application
High-speed signaling systems with adaptable pre-emphasis and equalization
AssigneeRambus Inc.
InventorsJared Zerbe, Fred Chen, Andrew Ho, Ramin Farjad-Rad, John Poulton, Kevin Donnelly, Brian Leibowitz
Life of this patent
Estimating the term…
Abstract
A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
Claims74
A system comprising:
- a. transmit pre-emphasis circuitry;
- b. a channel coupled to the transmit pre-emphasis circuitry;
- c. receiver coupled to the transmit pre-emphasis circuitry via the channel, the receiver having;
- i. a linear equalizer having a linear-equalizer input port coupled to the channel and a linear-equalizer output port;
- and
- ii. a decision-feedback equalizer coupled to the linear-equalizer output port.
3 more elements
A system comprising:
- a. first and second transmitters, each transmitter having a plurality of transmit taps, including a pre-cursor transmit tap, a cursor transmit tap, and a post-cursor transmit tap, coupled to respective ones of the driver input terminals;
- b. first and second channels coupled to the respective first and second transmitters;
- c. first and second receivers coupled to the first and second transmitters via the respective first and second channels, the first and second receivers each having a plurality of receive taps, including a post-cursor receive tap;
- d. tap-control logic coupled to the circuitry coupled to the receive taps, the tap-control logic disabling ones of the receive taps in the first receiver and enabling ones of the receive taps in the second receiver.
1 more element
A signaling system supporting a plurality of power and performance modes, including a high-performance mode and a low-performance mode, the signaling system comprising:
- a. a communication channel;
- b. a transmitter that includes:
- i. a transmit pre-emphasizer having a plurality of input terminals and an output port coupled to the communication channel;
- ii. a plurality of pre-emphasis taps coupled to respective ones of the plurality of input terminals, the pre-emphasis taps including a pre-cursor tap and a transmit post-cursor tap;
- and
- iii. a first mode-select port;
- c. a receiver coupled to the output port of the transmitter via the communication channel, the receiver including a receive equalizer having a receive post-cursor tap and a second mode-select port;
- and
- d. a controller coupled to the first and second mode-select ports.
6 more elements
A power-optimization method for a signaling system in which a transmitter communicates a data stream to a receiver, the method comprising:
- a. selecting a first power setting in which the transmitter and receiver collectively consume a first average power;
- b. monitoring an output of the receiver to determine an error rate for the data stream;
- and
- c. if the error rate is below a first error threshold, selecting a lower power setting in which the transmitter and the receiver collectively consume a lower average power than the first average power, else if the error rate is above a second error threshold, selecting a higher power setting in which the transmitter and the receiver collectively consume a higher average power than the first average power;
- d. wherein the transmitter, in the lower power setting, cancels inter-symbol-interference (ISI) from a number of post-cursor data symbols;
- and, in the higher power setting, cancels ISI from a lower number of post-cursor data symbols.
3 more elements
A circuit comprising:
- a. a first input node;
- b. a sampler having a second input node coupled to the first input node and a sampler output node;
- c. a first finite-impulse-response (FIR) filter having a first FIR input node coupled to the sampler output node, a first feedback node, and an FIR output node;
- d. a first feedback path extending from the first feedback node to the second input node;
- e. a second FIR filter having a second FIR input node coupled to the sampler output node, a second feedback node;
- and
- f. a second feedback path extending from the second feedback node to the second input node.
4 more elements
A partial-response DFE (PrDFE) comprising:
- a. a PrDFE input node;
- b. sample-select logic having a first select-logic input terminal, a second select-logic input terminal, and a select-logic output terminal;
- c. a first feed-forward path extending between the PrDFE input node and the first select-logic input terminal;
- d. a second feed-forward path extending between the PrDFE input node and the second select-logic input terminal;
- and
- e. a feedback path extending to a first feed-forward node in the first feed-forward path between the PrDFE input node and the first select-logic terminal and to a second feed-forward node in the second feed-forward path between the PrDFE input node and the second select-logic terminal.
3 more elements
A method of recovering, from a signal, a current symbol of a series of symbols, the method comprising:
- a. offsetting, during a clock cycle, the signal based upon a first filter coefficient selected to compensate for inter-symbol interference from a first preceding one of the symbols assuming the first preceding one of the symbols expresses a logic one, wherein offsetting the signal based upon the first filter coefficient produces a first corrected signal;
- b. offsetting, during the clock cycle, the signal based upon a second filter coefficient selected to compensate for inter-symbol interference from the first preceding one of the symbols assuming the first preceding one of the symbols expresses a logic zero, wherein offsetting the signal based upon the second filter coefficient produces a second corrected signal;
- c. offsetting the first and second corrected signals based upon a third filter coefficient selected to compensate for inter-symbol interference from a second preceding one of the symbols preceding the first preceding one of the symbols, wherein offsetting the first and second corrected signals based upon the third filter coefficient produces third and fourth corrected signals;
- d. sampling the third and fourth corrected signals to produce first and second alternative sampled signals;
- e. resolving the first preceding one of the symbols to obtain a resolved preceding symbol;
- and
- f. selecting the current symbol from among the first and second alternative sampled signals based upon the resolved preceding symbol.
4 more elements
An integrated circuit comprising a DFE, the integrated circuit comprising:
- a. a DFE input node;
- b. means for offsetting, during a clock cycle, a signal on the DFE input node based upon a first filter coefficient selected to compensate for inter-symbol interference from a first preceding one of the symbols assuming the first preceding one of the symbols expresses a logic one, wherein offsetting the signal based upon the first filter coefficient produces a first corrected signal;
- c. means for offsetting, during the clock cycle, the signal based upon a second filter coefficient selected to compensate for inter-symbol interference from the first preceding one of the symbols assuming the first preceding one of the symbols expresses a logic zero, wherein offsetting the signal based upon the second filter coefficient produces a second corrected signal;
- d. means for offsetting the first and second corrected signals based upon a third filter coefficient selected to compensate for inter-symbol interference from a second preceding one of the symbols preceding the first preceding one of the symbols, wherein offsetting the first and second corrected signals based upon the third filter coefficient produces third and fourth corrected signals;
- e. means for sampling the third and fourth corrected signals to produce first and second alternative sampled signals;
- and
- f. means for selecting one of the first and second alternative sampled signals.
4 more elements
A computer-readable medium having stored thereon a data structure defining a receiver adapted to receive an input signal expressed as a sequence of data symbols, the data structure comprising:
- a. first data representing a PrDFE having a PrDFE input node coupled to the DFE input node and a PrDFE output node;
- b. second data representing an FIR filter having an FIR input node coupled to the PrDFE output node and an FIR output node coupled to the PrDFE input node;
- and
- c. third data representing an intermediate feedback path coupled to the PrDFE output node and bypassing the FIR filter.
1 more element
A PrDFE comprising:
- a. a PrDFE input node;
- b. first and second power-supply terminals;
- b. a first sampler having a first sampler input port coupled to the PrDFE input node, a first sampler output port, a first sampler precharge section coupled between the first sampler output port and the first supply terminal, and a first sampler evaluate section coupled between the first sampler output port and the second supply terminal;
- c. a second sampler having a second sampler input port coupled to the PrDFE input node, a second sampler output port, a second sampler precharge section coupled between the second sampler output port and the first supply terminal, and a second sampler evaluate section coupled between the second sampler output port and the second supply terminal;
- and
- d. a multiplexer having a first multiplexer input port coupled to the first sampler output port, a second multiplexer input port coupled to the second sampler output port, a multiplexer output port, and at least one multiplexer select port, the multiplexer further including a multiplexer evaluate section coupled between the multiplexer output port and the first supply terminal and a multiplexer precharge section coupled between the multiplexer output port and the second supply terminal.
3 more elements
A circuit comprising:
- a. first and second power-supply terminals;
- b. a first sampler having a first sampler input port, a first sampler output port, a first sampler precharge section coupled between the first sampler output port and the first supply terminal, and a first sampler evaluate section coupled between the first sampler output port and the second supply terminal;
- c. a second sampler having a second sampler input port, a second sampler output port, a second sampler precharge section coupled between the second sampler output port and the first supply terminal, and a second sampler evaluate section coupled between the second sampler output port and the second supply terminal;
- and
- d. a multiplexer having a first multiplexer input port coupled to the first sampler output port, a second multiplexer input port coupled to the second sampler output port, a multiplexer output port and at least one multiplexer select port, the multiplexer further including a multiplexer evaluate section coupled between the multiplexer output port and the first supply terminal and a multiplexer precharge section coupled between the multiplexer output port and the second supply terminal.
2 more elements
A partial-response DFE comprising:
- a. an input node;
- b. a first feed-forward path extending from the input node and having a first sampler;
- b. a second feed-forward path extending from the input node having a second sampler;
- c. select logic having first and second select-logic input nodes, coupled to the respective first and second feed-forward paths, and a select-logic output node;
- and
- d. a split feedback path extending from the select-logic output node to each of the first and second feed-forward paths.
3 more elements
Dependencies are inferred from the claim text.