Laser control circuit and image forming apparatus
AssigneesKabushiki Kaisha Toshiba, Toshiba Tec Kabushiki Kaisha
InventorsDaisuke Ishikawa, Koji Tanimoto, Kenichi Komiya, Yuji Inagawa
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Abstract
An image data processing section subjects input image data to image processing, and outputs first to fourth image data. First to fourth pulse width modulation circuits are PWM circuits in each of which a plurality of reference positions are set in one pixel, and output pulses corresponding to the first to fourth image data. A synthesis circuit synthesizes the pulses output from the first to fourth pulse width modulation circuits, and a laser emits a light beam in accordance with the synthesized pulse.
Claims11
A laser control circuit comprising:
- a clock generation circuit which generates a reference clock signal;
- a synchronous circuit which includes a beam detection circuit detecting a light beam scanned in a main scanning direction and supplying a horizontal synchronous signal, and which supplies a synchronous clock synchronized with the horizontal synchronous signal on a basis of the reference clock signal;
- a first pulse width modulation circuit which outputs a pulse having a width corresponding to image data of an odd pixel output from an image data processing section in synchronization with the synchronous clock on a basis of at least one of first and second reference positions, the image data processing section being constituted to subject input image data to image processing and to output image data of odd pixel and even pixel in parallel;
- a second pulse width modulation circuit which outputs a pulse having a width corresponding to the image data of the even pixel output from the image data processing section in synchronization with the synchronous clock on a basis of at least one of first and second reference positions;
- and
- a synthesis circuit which synthesizes the pulses output from the first and second pulse width modulation circuits.
A laser control circuit comprising:
- a clock generation circuit which generates a reference clock signal;
- a first synchronous circuit which includes a beam detection circuit detecting a light beam scanned in a main scanning direction and supplying a horizontal synchronous signal, and which supplies a first clock synchronized with the horizontal synchronous signal, on a basis of a reference clock signal from the clock generation circuit;
- a delay circuit which supplies a delayed horizontal synchronous signal obtained by delaying the horizontal synchronous signal by a half period of the first clock;
- a second synchronous circuit which supplies a second clock synchronized with the delayed horizontal synchronous signal on a basis of the reference clock signal;
- an image data processing section which subjects input image data to image processing and which outputs first to fourth image data in parallel;
- a first pulse width modulation circuit which outputs a pulse having a width corresponding to the first image data as an odd-numbered pixel with a left reference in accordance with the first clock;
- a second pulse width modulation circuit which outputs a pulse having a width corresponding to the second image data as an odd-numbered pixel with a right reference in accordance with the first clock;
- a third pulse width modulation circuit which outputs a pulse having a width corresponding to the third image data as an even-numbered pixel with the left reference in accordance with the second clock;
- a fourth pulse width modulation circuit which outputs a pulse having a width corresponding to the fourth image data as an even-numbered pixel with the right reference in accordance with the second clock;
- a synthesis circuit which synthesizes the pulses output from the first to fourth pulse width modulation circuits;
- and
- a laser which emits a light beam in accordance with the pulse synthesized by the synthesis circuit.
An image forming apparatus comprising:
- a beam detection circuit which detects a light beam scanned in a main scanning direction and which supplies a horizontal synchronous signal;
- a clock generation circuit which generates a reference clock signal;
- a synchronous circuit which supplies a synchronous clock synchronized with the horizontal synchronous signal on a basis of the reference clock signal;
- an image data processing section which subjects input image data to image processing and which outputs image data of odd and even pixels in parallel;
- a first pulse width modulation circuit which outputs a pulse having a width corresponding to the image data of the odd pixel output from the image data processing section in synchronization with the synchronous clock on a basis of at least one of first and second reference positions;
- a second pulse width modulation circuit which outputs a pulse having a width corresponding to the image data of the even pixel output from the image data processing section in synchronization with the synchronous clock on a basis of at least one of first and second reference positions;
- a synthesis circuit which synthesizes the pulses output from the first and second pulse width modulation circuits;
- a laser which emits a light beam in accordance with the pulse synthesized by the synthesis circuit;
- and
- an image forming section which forms an image on a basis of the light beam emitted by the laser.
Dependencies are inferred from the claim text.