Phase estimation method in a digital and phase locked loop communication system
AssigneeST Microelectronics SA
InventorsJean-Marc Brossier, Frederic Lehmann
Life of this patent
Estimating the term…
Abstract
A method for estimating the phase in a digital communication system, comprising the steps of: receiving and storing a block of observations Yk; executing at least one phase locked loop (PLL) on a predetermined sequence of observations extracted from said block. Each PLL provides an intermediate value, combining both intermediate values makes it possible to provide a sharpened phase estimate. The method allows realization of an improved phase estimator based on the simplicity of phase locked loops.
Claims10
A method for estimating the phase in a digital communication system comprising the steps of:
- receiving and storing a block of observations Yk;
- executing at least one phase locked loop (PLL) on a predetermined sequence of observations from said block.
A method according to any of the preceding claims characterized in that the modulation is a binary phase shift keying (BPSK) modulation with a phase locked loop (PLL) defined by
- φK=φk−1+γlmg(yke−iφ(k−1)th[Lk/2+2/φ2Re(yke−lφ(k−1)])
- where:
- th is the hyperbolic tangent operator,
- Re is the operator referring to the real part of a complex number,
- σ2 is the noise variance;
- and Lk=Ln [p(ak=1)/p(ak=−1)],
- and Ln is the natural logarithm, p(ak=1) is the probability that symbol ak is equal to +1 and p(ak=−1) is the probability that symbol ak is equal to −1.
A phase locked loop device for a digital receiver comprising:
- means to receive and store blocks of observations;
- a first phase locked loop (PLL) for generating a first intermediate value;
- a second phase locked loop (PLL) for generating a second intermediate value;
- means to derive a phase estimate form said first and second intermediate values.
Dependencies are inferred from the claim text.