Nonvolatile ferroelectric memory and control device using the same
AssigneeHynix Semiconductor Inc.
InventorHee Kang
Life of this patent
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Abstract
A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption.
Claims18
1-11. (canceled)
A nonvolatile ferroelectric memory comprising a plurality of unit blocks,
- wherein each unit block comprises a plurality of cell arrays, a plurality of row decoders and a plurality of column pages, and
- the plurality of column pages in one unit block constitute a unit block page to be activated simultaneously.
A nonvolatile ferroelectric memory comprising:
- a plurality of unit blocks each comprising a plurality of cell arrays;
- a common data bus unit for exchanging input/output data with the plurality of unit blocks;
- a unit block page comprising a plurality of column pages;
- and
- a data bus unit for exchanging input/output data with the unit block page,
- wherein the plurality of column pages in the unit block page are activated simultaneously.
A nonvolatile ferroelectric memory comprising:
- a page address latch for latching a page address in response to a chip enable signal;
- a row address latch unit for latching a row address in response to the chip enable signal, and outputting the latched row address;
- an address transition detector for detecting transition of the latched row address, and outputting an address transition detecting signal;
- a chip control generator for selectively generating a control signal to control a chip operation in response to the address transition detecting signal;
- and
- a plurality of unit blocks, each unit block comprising a plurality of cell arrays, a plurality of row decoders and a plurality of column pages, wherein the plurality of column pages in one unit block constitute a unit block page to be activated simultaneously.
A nonvolatile ferroelectric memory comprising:
- a page address latch for latching a page address in response to a chip enable signal;
- a row address latch unit for latching a row address in response to the chip enable signal, and for outputting the latched row address;
- an address transition detector for detecting transition of the latched row address, and for outputting an address transition detecting signal;
- a chip control signal generator for selectively generating a control signal to control a chip operation in response to the address transition detecting signal;
- a plurality of unit blocks comprising a plurality of cell arrays;
- a common data bus unit for exchanging input/output data with the plurality of unit blocks;
- a unit block page comprising a plurality of column pages;
- and
- a data bus unit for exchanging input/output data with the unit block page,
- wherein the plurality of column pages in the unit block page are activated simultaneously.
Dependencies are inferred from the claim text.