System and method for mode register control of data bus operating mode and impedance

A method of controlling the operation of a memory device having a plurality of data bus terminals, the method comprising:

• driving the data bus terminals to either a first or a second voltage when read data signals are to be applied to the data bus terminals in a first operating mode;
• and
• driving the data bus terminals to either a third or a fourth voltage when read data signals are to be applied to the data bus terminals in a second operating mode;
• and
• programming the memory device to operate in either the first operating mode or the second operating mode.

A system for controlling the operation of a plurality of data bus terminals in a memory device, the system comprising:

• a mode register programmable to select either a first mode or a second mode of operation for the data bus terminals, the mode register being operable to output a mode control signal corresponding to the selected mode;
• a timing circuit coupled to receive the mode control signal from the mode register, the timing circuit receiving a clock signal and generating timing signals corresponding to the selected one of the first and second modes in synchronism with the clock signal;
• a data timing circuit coupled to the timing circuit, the data timing circuit receiving read data signals and generating timed data signals corresponding to the read data signals;
• data bus terminal drive logic coupled to the data timing circuit, the data bus terminal drive logic generating output signals responsive to the timed data signals;
• and
• pull-up and pull-down circuitry coupled to the data bus terminal drive logic, the pull-up and pull-down circuitry being operable to drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected.

A memory device, comprising:

• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• an array of memory cells operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a write data path circuit operable to couple write data signals from the external data bus terminals of the memory device and to couple the write data signals the array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals, the command decoder including a mode register programmable to select either a first mode or a second mode of operation for the data bus terminals, the mode register being operable to output a mode control signal corresponding to the selected mode;
• and
• a read data path circuit operable to couple read data signals from the array to the external data bus terminals of the memory device, the read data path comprising:
• a timing circuit coupled to receive the mode control signal from the mode register, the timing circuit receiving a clock signal and generating timing signals corresponding to the selected one of the first and second modes in synchronism with the clock signal;
• a data timing circuit coupled to the timing circuit, the data timing circuit receiving read data signals and generating timed data signals corresponding to the read data signals;
• data bus terminal drive logic coupled to the data timing circuit, the data bus terminal drive logic generating output signals responsive to the timed data signals;
• and
• pull-up and pull-down circuitry coupled to the data bus terminal drive logic, the pull-up and pull-down circuitry being operable to drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected.

A processor-based system, comprising

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a dynamic random access memory device coupled to the processor bus adapted to allow data to be stored, the dynamic random access memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminals;
• an array of dynamic random access memory cells operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
• a write data path circuit operable to couple write data signals from the external data bus terminals of the memory device and to couple the write data signals the array;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals, the command decoder including a mode register programmable to select either a first mode or a second mode of operation for the data bus terminals, the mode register being operable to output a mode control signal corresponding to the selected mode;
• and
• a read data path circuit operable to couple read data signals from the array to the external data bus terminals of the memory device, the read data path comprising:
• a timing circuit coupled to receive the mode control signal from the mode register, the timing circuit receiving a clock signal and generating timing signals corresponding to the selected one of the first and second modes in synchronism with the clock signal;
• a data timing circuit coupled to the timing circuit, the data timing circuit receiving read data signals and generating timed data signals corresponding to the read data signals;
• data bus terminal drive logic coupled to the data timing circuit, the data bus terminal drive logic generating output signals responsive to the timed data signals;
• and
• pull-up and pull-down circuitry coupled to the data bus terminal drive logic, the pull-up and pull-down circuitry being operable to drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected.