Semiconductor device and display device utilizing the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorHajime Kimura
Life of this patent
Estimating the term…
Abstract
A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.
Claims86
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- a switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the switch;
- and
- means for short-circuiting between the first terminal of the first transistor and the second terminal of the first transistor,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- and
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- and
- a first switch and a second switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the first switch,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor;
- and
- wherein the first terminal of the first transistor and the second terminal of the first transistor are connected via the second switch.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- and
- a switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the switch;
- and
- means for short-circuiting between the first terminal of the second transistor and the second terminal of the second transistor,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- and
- a first switch and a second switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the first switch,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor;
- and
- wherein the first terminal of the second transistor and the second terminal of the second transistor are connected via the second switch.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- a first switch, a second switch, and a third switch, wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the first switch;
- and
- a wiring,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor via a second switch;
- and
- wherein the gate terminal of the second transistor is connected to the wiring via a third switch.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- and
- a switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the switch;
- and
- means for short-circuiting at least either of between the first terminal of the first transistor and the second terminal of the first transistor or between the first terminal of the second transistor and the second terminal of the second transistor,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor.
A semiconductor device comprising:
- a first transistor comprising a gate terminal, a first terminal, and a second terminal;
- a second transistor comprising a gate terminal, a first terminal, and a second terminal;
- a first switch and a second switch wherein the gate terminal of the first transistor and the first terminal of the first transistor are connected via the first switch,
- wherein the second terminal of the first transistor is connected to the first terminal of the second transistor;
- wherein the gate terminal of the first transistor is connected to the gate terminal of the second transistor;
- and
- wherein the second switch is disposed at least either of between the first terminal of the first transistor and the second terminal of the first transistor or between the first terminal of the second transistor and the second terminal of the second transistor.
Dependencies are inferred from the claim text.