US 2006/0187728 A1 · Integrated semiconductor memory

Abstract

An integrated semiconductor memory (100) comprises a controllable voltage generator (30) for precharging bit lines (BL) of a memory cell array (10) to a precharge voltage (VEQ). During the read-out of a first and second memory state of memory cells (SZ) which are connected to the bit lines, a first and second signal swing (ΔUH, ΔUL) occurs on the bit lines, as a result of which the bit lines are charged to a first and a second voltage potential (V1, V2). For the purpose of precharging the bit lines to the precharge voltage (VEQ), a first equalize current (I1) and a second equalize current (I2) are fed onto the bit lines by the controllable voltage generator (30), the current intensity of said currents in each case being measured by a detector circuit (60). A control circuit (20) alters the precharge voltage (VEQ) until the first and second equalize currents (I1, I2) have identical magnitudes. The precharge voltage is then centered with respect to the first and second voltage potentials (V1, V2).

Claims19

Dependent claims

An integrated semiconductor memory comprising:

a memory cell coupled to a bit line, wherein the bit line, for the purpose of charging to a precharge voltage, can be coupled to a terminal for application of the precharge voltage;
a control circuit for providing a control signal at an output;
a controllable voltage generator with an input terminal coupled to the output of the control circuit for the controllable voltage generator including an output terminal for providing the precharge voltage, wherein the controllable voltage generator is designed in such a way that it generates the precharge voltage at the output terminal in a manner dependent on the control signal;
and
a detector circuit for measuring an equalize current between the output terminal of the controllable voltage generator and the terminal for application of the precharge voltage, wherein the equalize current measured by the detector circuit can be fed to the control circuit, and wherein the control circuit is designed in such a way that it generates the control signal for driving the controllable voltage generator in a manner dependent on the magnitude of the measured equalize current.

2 more elements

A method for operating an integrated semiconductor memory, comprising:

providing an integrated semiconductor memory comprising a memory cell for storing a first or a second memory state that can be connected to a bit line for the purpose of reading the first or second memory state in and out, and comprising a controllable voltage generator that generates an equalize current for the purpose of precharging the bit line to a desired value of a precharge voltage;
storing the first memory state in the memory cell;
subsequently precharging the bit line to the desired value of the precharge voltage;
subsequently coupling the memory cell to the bit line and generating a first voltage potential on the bit line;
subsequently generating a first equalize current using the controllable voltage generator for the purpose of precharging the bit line to the desired value of the precharge voltage;
subsequently measuring a magnitude of the first equalize current;
subsequently storing the second memory state in the memory cell;
subsequently precharging the bit line to the desired value of the precharge voltage;
subsequently coupling the memory cell to the bit line and generating a second voltage potential on the bit line;
subsequently generating a second equalize current using the controllable voltage generator for the purpose of precharging the bit line to the desired value of the precharge voltage;
subsequently measuring the magnitude of the second equalize current;
and
subsequently altering the desired value of the precharge voltage in a manner dependent on the magnitude of the first and second equalize currents.

10 more elements

Dependencies are inferred from the claim text.

Integrated semiconductor memory

Life of this patent

Integrated semiconductor memory

Life of this patent

Abstract

Claims19