Test for weak sram cells

Apparatus for testing a static random access memory (SRAM) array for the presence of weak cells, the memory array comprising a plurality of SRAM cells each having an initial logic state, a pair of bit lines (BL, BLB) to which each SRAM cell is connected, each SRAM cell being coupled to a respective word line (WL), the apparatus comprising means for pre-charging at least one of said bit lines (BL, BLB) to a predetermined level, means for enabling said word lines (WL), means for driving at least one of said bit lines, or a node voltage proportional thereto, to a predetermined trip voltage, means for identifying the logic state of each of the SRAM cells after said at least one bit line, or node voltage proportional thereto, has been driven to said predetermined trip voltage to determine if the logic state of any of the cells has changed from said initial logic state, and means for marking or otherwise identifying as weak those cells whose logic state has been determined to have changed from said initial logic state;

• characterized in that said means for enabling said word lines comprises means for enabling substantially simultaneously all of said word lines in said memory array.

Apparatus according to any one of the preceding claims, comprising means for shorting together said bit lines (BL, BLB) after said word line(s) has (have) been enabled.

A method for testing a static random access memory (SRAM) array for the presence of weak cells, the memory array comprising a plurality of SRAM cells each having an initial logic state, a pair of bit lines (BL, BLB) to which each SRAM cell is connected, each SRAM cell being coupled to a respective word line (WL), the method comprising the steps of pre-charging at least one of said bit lines to a predetermined level, enabling said word lines, driving at least one of said bit lines, or a node voltage proportional thereto, to a predetermined trip voltage, identifying the logic state of each of the SRAM cells after said at least one bit line, or node voltage proportional thereto, has been driven to said predetermined trip voltage to determine if the logic state of any of the cells has changed from said initial logic state, and marking or otherwise identifying as weak those cells whose logic state has been determined to have changed from said initial logic state;

• characterized in that said step of enabling said word lines comprises enabling substantially simultaneously all of said word lines in said memory array.