Nonvolatile semiconductor memory device having improved redundancy relieving rate
AssigneeRenesas Technology Corp.
InventorTsukasa Ooishi
Life of this patent
Estimating the term…
Abstract
In a memory cell array of an MRAM, a normal memory cell is compared with a reference memory cell which holds a reference value, thereby storing data of one bit per cell. Two spare memory cells store data of one bit as a whole. By writing complementary values to the two spare memory cells and connecting these spare memory cells to a sense amplifier, the stored data of one bit is read. A spare memory cell section which is often arranged in an array peripheral portion becomes more resistant against a variation in finished dimensions of elements and a success rate for replacing and relieving a defective memory cell by a spare memory cell increases.
Claims4
A nonvolatile semiconductor memory device comprising:
- a plurality of normal memory cells each storing data of one bit in a nonvolatile manner;
- a plurality of spare memory cells each used in place of a defective memory cell when the defective memory cell is present in said plurality of normal memory cells, and constituted so that two spare memory cells store data of one bit as a whole;
- a control circuit, in accordance with an external access, selecting a first memory cell group corresponding to an address signal from among said plurality of normal memory cells and selecting a second memory cell group from among said plurality of spare memory cells in parallel to selection of said first memory cell group;
- and
- a select and amplification section selecting a read memory cell group in accordance with said address signal from among said first and second memory cell groups, and amplifying and outputting the data held in said read memory cell group.
Dependencies are inferred from the claim text.