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US 2006/0187720 A1Published application
Semiconductor device
AssigneeHitachi, Ltd.
InventorsSatoru Hanzawa, Takeshi Sakata
Life of this patent
Estimating the term…
Abstract
A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
Claims9
1-23. (canceled)
A semiconductor device comprising:
- a data line;
- a plurality of memory cells coupled to the data line and storing a first information or a second information according to write data;
- a dummy data line;
- a plurality of first dummy cells and second dummy cells coupled to the dummy data line, the plurality of first dummy cells storing the first information and the plurality of second dummy cells storing the second information;
- a first load circuit coupled between the data line and a first voltage;
- a second load circuit coupled between the dummy data line and the first voltage;
- and
- a third load circuit coupled between the dummy data line and the first voltage,
- wherein a signal read out from a selected one of the plurality of memory cells is inputted to the first load circuit, and
- wherein a signal read out from a selected one of the plurality of first dummy cells and a selected one of the plurality of second dummy cells is inputted to the second load circuit and the third load circuit.
7 more elements
Dependencies are inferred from the claim text.