Reduction of adjacent floating gate data pattern sensitivity
AssigneeMicron Technology, Inc.
InventorFrankie Roohparvar
Life of this patent
Estimating the term…
Abstract
The method for programming non-volatile memory cells erases the memory cells to be programmed. The memory cells are then programmed to a reduced floating gate voltage that takes into account capacitive coupling between the floating gates of adjacent memory cells. In one embodiment, the programming method programs and verifies a first memory cell to the reduced floating gate voltage, programs and verifies an adjacent memory cell to the reduced floating gate voltage, and verifies the first memory cell to an increased floating gate voltage that is greater than the reduced floating gate voltage.
Claims18
A flash memory device comprising:
- a memory array arranged in rows and columns such that the rows comprise wordlines coupled to control gates of a plurality of memory cells and the columns comprise bitlines coupled to series strings of memory cells;
- and
- control circuitry that is adapted to control programming of the memory cells by erasing at least a first memory cell of the memory array and programming the first memory cell such that a coupling effect from an adjacent memory cell is taken into account.
An electronic system comprising:
- a processor that generates memory device control signals;
- and
- a memory device, coupled to the processor, that is adapted to be programmed and erased in response to the control signals, the memory device comprising:
- a memory array arranged in rows and columns such that the rows comprise wordlines coupled to control gates of a plurality of memory cells and the columns comprise bitlines coupled to series strings of memory cells;
- and
- control circuitry that is adapted to control programming of the memory cells by erasing at least a first memory cell of the memory array and programming the first memory cell such that a coupling effect from adjacent memory cells is taken into account.
A non-volatile memory device comprising:
- a non-volatile memory array arranged in rows and columns such that the rows comprise wordlines coupled to a plurality of memory cells and the columns comprise bitlines coupled to series strings of memory cells;
- and
- control circuitry that is adapted to control programming of the memory cells by erasing a first set of memory cells of the memory array and programming the first set of memory cells such that a coupling effect from an adjacent memory cell is taken into account.
Dependencies are inferred from the claim text.