Twin insulator charge storage device operation and its fabrication method
AssigneeHalo LSI, Inc.
InventorsSeiki Ogura, Kimihiro Satoh, Tomoya Saito
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Abstract
The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.
Claims3
An operation method for a twin MONOS memory comprising:
- polysilicon control gates on a substrate having an oxide-nitride-oxide (ONO) layer underlying said control gates wherein said nitride portion of said ONO layer underlying said control gates provides memory storage;
- memory diffusions within said substrate between each two of said control gates wherein said memory diffusions are connected to adjacent diffusions alternately by a local wiring overlying said substrate;
- and
- metal bit lines crossing said control gates and isolated by shallow trench isolation (STI) lines to complete said Twin MONOS memory device
- wherein said operation method comprises multi-level programming comprising:
- controlling a threshold voltage of a selected memory cell by adjusting a voltage of said control gate or said bit line.
Dependencies are inferred from the claim text.