Non-volatile memory array with simultaneous write and erase feature

A non-volatile memory array comprising,

• a plurality of memory cells in rows and columns, each cell having a non-volatile memory transistor with a source, drain, and channel and an auxiliary transistor means for generating space charge for programming the non-volatile memory transistor;
• and
• a word line in capacitive relation to a first row of memory cells of the array via a plurality of capacitive plates, each of the plurality of capacitive plates comprising a first region of the word line forming a control gate for a memory transistor.

A non-volatile memory array having a plurality of memory cells in rows and columns comprising:

• a non-volatile memory transistor in each cell with a source, drain, and channel;
• an injector transistor associated with each cell having means for generating space charge for use with an associated non-volatile memory transistor, and
• a plurality of word lines, each word line having a plurality of capacitive plates, each of the plurality of capacitive plates having a first region forming a control gate for a memory transistor in one row and a second region forming a control gate for an injector transistor in another row.