2-Transistor floating-body dram
AssigneeIntel Corporation
InventorsStephen Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad Khellah, Yibin Ye, Shih-Lien Lu, Vivek De
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
Claims45
A memory cell, comprising:
- a first transistor having a floating channel body and a gate terminal coupled to a first word line;
- and
- a second transistor coupled between the first transistor and a bit line and having a gate terminal to receive a signal from a second word line and another terminal coupled to a source or drain of the first transistor, wherein a turn-on state of the second transistor is controlled to isolate data stored in the floating channel body from a voltage applied to the bit line during a predetermined condition.
(canceled)
A memory cell, comprising:
- a first transistor having a floating channel body;
- and
- a second transistor coupled between the first transistor and a bit line wherein a turn-on state of the second transistor is controlled to isolate data stored in the floating channel body from a voltage applied to a bit line during a predetermined condition, and wherein a gate of the second transistor is to assume a first voltage state when a first value is written into the floating channel body and is to assume a second voltage state when a second value is written in to the floating channel body
A memory cell, comprising:
- a first transistor having a floating channel body;
- and
- a second transistor coupled between the first transistor and a bit line,
- wherein the second transistor provides a level of isolation between the first transistor and the bit line sufficient to allow a gate of the first transistor to assume different voltage states during write “1” and write “0” operations.
A method for controlling a memory, comprising:
- adjusting voltage of a word line to place a cell in an unselected state;
- and
- controlling a circuit between a first transistor of the unselected cell and a bit line, to isolate data stored in a floating body of the first transistor from a voltage applied to the bit line during a predetermined condition, wherein a gate of the first transistor assumes a first voltage state during the write “1” operation of the selected memory cell, said first voltage state being higher than a second voltage state the bit line assumes when a write “0” operation is performed for the unselected cell.
26-27. (canceled)
A method for controlling a memory, comprising:
- adjusting voltage of a word line to place a cell in an unselected state;
- and
- controlling a circuit between a first transistor of the unselected cell and a bit line, to isolate data stored in a floating body of the first transistor from a voltage applied to the bit line during a predetermined condition, wherein the circuit includes a second transistor having a polarity different from the first transistor and wherein controlling the circuit includes:
- controlling a turn-on state of the second transistor based on a voltage state of a control line which is separate from the word line.
A method of controlling a memory, comprising:
- adjusting voltage of a word line to switch a cell between selected and unselected states;
- and
- controlling activation of a circuit between a bit line and a first floating-body transistor in the cell, to provide a level of isolation between the first transistor and bit line sufficient to allow a gate of the first transistor to assume different voltage levels during write “1” and write “0” operations.
A system, comprising:
- a controller;
- and
- a memory cell including:
- (a) a first transistor having a floating channel body and a gate terminal coupled to a first word line;
- and
- (b) a second transistor coupled between the first transistor and a bit line, and having a gate terminal to receive a signal from a second word line and another terminal coupled to a source or drain of the first transistor, wherein the controller controls a turn-on state of the second transistor to isolate data stored in the floating channel body from a voltage applied to the bit line.
Dependencies are inferred from the claim text.