Memory integrated circuit, in particular an SRAM memory integrated circuit, and corresponding fabrication process
AssigneeSTMicroelectronics S.r.l.
InventorFrancois Jacquet
Life of this patent
Estimating the term…
Abstract
A RAM memory integrated circuit, in particular a SRAM memory integrated circuit, includes a matrix of memory cells that are arranged between two bit lines via two access transistors. The bit lines are intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation. The bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines. The memory cells of each column are implanted in the form of groups of cells which are alternately connected to one or the other of the partial bit lines, respectively.
Claims20
A memory integrated circuit, in particular an SRAM memory integrated circuit, comprising:
- a matrix of memory cells that are arranged in rows and columns of memory cells between two bit lines via two respective access transistors, the bit lines being intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation, wherein the bit line of each column of the matrix that is intended to be maintained at the high precharge potential is produced in the form of at least two partial bit lines, the memory cells of each column being implanted in the form of groups of cells connected to the partial bit lines, respectively.
A process for fabricating a memory integrated circuit, in particular an SRAM memory integrated circuit, the circuit comprising a matrix of memory cells that are arranged in rows and columns of memory cells between two bit lines via two respective access transistors, the bit lines being intended in one case to be discharged and in the other case to be maintained at a high precharge potential during a read operation, comprising:
- producing the bit lines of each column of the matrix in the form of partial bit lines to which respective groups of memory cells of the column are connected.
An integrated circuit memory, comprising:
- a bit line;
- a column of memory cells divided into at least a first, second, third and fourth group of cells;
- a plurality of access transistors coupling the memory cells to the bit line;
- wherein the bit line comprises a first partial bit line and a second partial bit line each extending along the column, the first partial bit line coupled through access transistors to the first and third groups of cells and the second partial bit line coupled through access transistors to the second and fourth groups of cells.
An integrated circuit memory, comprising:
- a plurality of memory cells in a column;
- and
- a bit line coupled to the memory cells in the column, the bit line comprising first and second segments each extending along the column of memory cells, the first and second segments each divided into successive line segment portions, which line segment portions alternatively couple to groups of memory cells along the column.
An integrated circuit memory, comprising:
- a matrix of SRAM memory cells wherein each row of SRAM memory cells lies between and is coupled to complementary bit lines via two respective access transistors, each complementary bit line being produced in the form of two partial bit lines, the SRAM memory cells of each column comprising plural groups of cells, wherein alternate groups of cells are connected to one or the other of the two partial bit lines, and each partial bit line is formed of consecutive portions wherein alternate portions lie in different metallization layers of the integrated circuit memory.
Dependencies are inferred from the claim text.