US 2006/0187701 A1Published application

Integrated semiconductor memory with an arrangement of nonvolatile memory cells, and method

AssigneeInfineon Technologies AG

InventorCorvin Liaw

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Abstract

In integrated semiconductor memories whose stored information is represented by the magnitude of the ohmic resistance of layer stacks with a respective layer comprising a solid electrolyte, the problem arises that although the fact that the large threshold values (G1, G2) for the writing voltage and the erasure voltage differ from memory cell to memory cell means that the memory cells can be programmed individually, said memory cells cannot conventionally be erased individually, i.e., selectively in relation to the other memory cells. The reason for this is the large bandwidth of the threshold values (G1) for the erasure voltages, which ranges from a potential (Verasemin) to a potential (Verasemax). The invention proposes a semiconductor memory and a method for operating the latter, in which simultaneous biasing of all the bit lines and word lines and a specific choice of the electrical potentials allow a single memory cell to be erased selectively in relation to the other memory cells.

Claims25

Dependent claims

An integrated semiconductor memory comprising:

a plurality of nonvolatile memory cells;
and
a plurality of first lines and second lines that can be electrically biased for the purpose of programming and erasing the memory cells;
wherein each memory cell is coupled to a respective first line and a respective second line and includes a layer stack that has a solid electrolyte and that is arranged between the respective first line and the respective second line;
wherein the layer stacks in the memory cells are in a form such that their resistance can be altered by the level of a voltage applied between the respective first line and the respective second line and assumes a first value at a sufficiently high positive voltage and a different, second value at a sufficiently high negative voltage;
wherein the first lines and the second lines can be actuated such that electrical potentials on the first lines and on the second lines are changed, for the purpose of selectively erasing a selected memory cell selectively in relation to all the other memory cells in the arrangement of memory cells, such that, respectively, that first line to which the selected memory cell is coupled is biased with a first potential selectively in relation to all the other first lines, and that second line to which the selected memory cell is coupled is biased with a second potential selectively in relation to all the other second lines, and all the other first lines are biased with a third potential and all the other second lines are biased with a fourth potential;
wherein a potential difference between the first potential and the second potential is greater than a limit value for an erasure voltage, above which limit value any memory cell in the arrangement is reliably erased;
and
wherein the third and the fourth potential are proportioned such that, during the selective erasure of the selected memory cell, voltages applied to the other memory cells are so low that erasure operations and programming operations in the other memory cells are prevented.

6 more elements

A method for operating an integrated semiconductor memory, the method comprising:

providing an array of memory cells arranged in rows and columns, each memory cell in a row coupled to one of a plurality of first lines and each memory cell in a column coupled to one of a plurality of columns, each of the memory cell including a solid electrolyte disposed between one of the first lines and one of the second lines;
biasing a selected first line to a first potential;
biasing a selected second line to a second potential, wherein a potential difference between the first potential and the second potential is greater than a limit value for an erasure voltage, above which limit value a selected memory cell is reliably erased, the solid electrolyte of the selected memory cell disposed between the selected first line and the selected second line;
biasing unselected first lines to a third potential;
and
biasing unselected second lines to a fourth potential, wherein the third potential and the fourth potential are proportioned such that, during erasure of the selected memory cell, voltages applied to unselected memory cells are such that erasure operations and programming operations in the unselected memory cells are prevented;
whereby the selected memory cell is erased selectively in relation to the unselected memory cells.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/341,902Filed 27 Jan 2006
Priority: DE 10 2005 004 107.828 Jan 2005
Published: 24 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G11C 13/0011
RRAM elements whose operation depends upon chemical change: comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
G11C 13/0069
Auxiliary circuits: writing or programming circuits or methods
G11C 2013/009
Writing or programming circuits or methods: write using potential difference applied between cell electrodes
G11C 2213/77
Resistive array aspects: array wherein the memory element being directly connected to the bit lines and word lines without any access device being…