Single event effect (SEE) tolerant circuit design strategy for SOI type technology
AssigneeIota Technology, Inc.
InventorIu-Meng Ho
Life of this patent
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Abstract
A method of designing an integrated circuit to be Single Event Upset (SEU) immune by converting one or more Single Event Transient (SET) sensitive transistors into at least two serially connected transistors, and spacing the transistors sufficiently far apart so that the probability of a specified high-energy particle striking both transistors at the same time is remote.
Claims19
A method of designing an integrated circuit to be Single Event Upset (SEU) immune, said integrated circuit having one or more Single Event Transient (SET) sensitive transistors, said method comprising:
- converting one or more of said one or more Single Event Transient (SET) sensitive transistors into at least two serially connected transistors;
- and
- spacing said at least two transistors sufficiently far apart so that the probability of a specified high-energy particle striking both transistors at the same time is remote.
A method of manufacturing a Single Event Upset (SEU) immune integrated circuit, said method comprising:
- providing a design for an integrated circuit, said integrated circuit comprising a Single Event Transient (SET) sensitive transistor;
- and
- inserting a serially connected transistor pair for said SET transistor, wherein the transistors in said transistor pair are separated by a distance such that the probability of a high-energy particle of a predetermined energy striking both transistors at the same time is remote.
Dependencies are inferred from the claim text.