ROM with a partitioned source line architecture
AssigneeVirage Logic Corporation
InventorAmit Khanuja
Life of this patent
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Abstract
A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.
Claims26
A memory operation method associated with a Read-Only Memory (ROM) circuit, said ROM circuit having a plurality of ROM cells organized in an array of M rows and N columns, wherein each of said N columns is associated with a precharged source line that is partitioned into a number of source line segments based on a number of row banks of said array:
- based on row address signals provided to said ROM circuit with respect to accessing a ROM cell location, generating a Bank Select (BS) signal corresponding to said ROM cell location's row;
- and
- based on column address signals provided to said ROM circuit with respect to accessing said ROM cell location and on said BS signal, deactivating a source line segment associated with said ROM cell location, thereby developing a read voltage differential on a global bitline associated therewith for sensing.
A Read-Only Memory (ROM) circuit having a plurality of ROM cells organized in an array of M rows and N columns, wherein each of said N columns is associated with a precharged source line that is partitioned into a number of source line segments based on a number of row banks of said array, said ROM circuit comprising:
- means, responsive to row address signals provided to said ROM circuit with respect to accessing a ROM cell location, for generating a Bank Select (BS) signal corresponding to said ROM cell location's row;
- and
- means, responsive to column address signals provided to said ROM circuit with respect to accessing said ROM cell location and to said BS signal, for deactivating a source line segment associated with said ROM cell location, whereby a read voltage differential is developed on a global bitline associated therewith for sensing.
A Read-Only Memory (ROM) circuit, comprising:
- a plurality of ROM cells organized as an array having M rows and N columns, wherein said M rows are grouped into K banks;
- and
- a partitioned source line associated with each of said N columns, said partitioned source line including a plurality of source line segments, each segment being decodable based on a Bank Select (BS) signal that is operable to select a bank and on a column address for selecting a particular column of said N columns.
A memory compiler for compiling at least one Read-Only Memory (ROM) instance, comprising:
- a code portion for generating a plurality of ROM cells organized as an array of M rows and N columns, wherein said M rows are grouped into K banks;
- and
- a code portion for generating a partitioned source line associated with each of said N columns, said partitioned source line including a plurality of source line segments wherein each segment is decodable based on a Bank Select (BS) signal that is operable to select a bank and on a column address for selecting a particular column of said N columns.
Dependencies are inferred from the claim text.