Video signal processing apparatus
AssigneePanasonic Corporation
InventorSatoru Tanigawa
Life of this patent
Estimating the term…
Abstract
A video signal processing apparatus is provided with a first clock generation circuit for generating a first clock synchronized with an input signal; a second clock generation circuit for receiving a set value to be a reference of an output frequency, adding the set value for every reference clock, extracting data according to the cumulative value, converting the data into an analog signal, reducing quantization noise, and multiplying the analog signal, thereby to obtain a second clock; and a clock switch circuit for generating a sync signal that is switched to the second clock, by using a sync signal generated with the first clock; and video signal processing is carried out using the second clock that is generated according to the resolution of a pixel display.
Claims6
A video signal processing apparatus comprising:
- a first clock generation circuit for generating a first clock synchronized with an input signal;
- a first video signal processing circuit for performing video signal processing using the first clock;
- a second clock generation circuit for generating a second clock according to a resolution of a pixel display;
- a writing control circuit for controlling writing of data into a memory by the first clock;
- a clock switch circuit for generating a sync signal that is switched to the second clock, using the sync signal generated with the first clock;
- a reading control circuit for controlling reading of data outputted from the memory, using the second clock;
- and
- a second video signal processing circuit for performing video signal processing using the second clock.
A video signal processing apparatus comprising:
- a first clock generation circuit for generating a first clock synchronized with an input signal, using a reference clock outputted from a clock oscillation circuit;
- a first video signal processing circuit for performing video signal processing using the first clock;
- a second clock generation circuit for generating a second clock according to a resolution of a pixel display;
- a third clock generation circuit for generating a third clock by multiplying the reference clock by M (M:
- integer);
- a first writing control circuit for controlling writing of data into a first memory by the first clock;
- a first clock switch circuit for generating a sync signal that is switched to the third clock, using the sync signal generated with the first clock;
- a first reading control circuit for controlling reading of data from the first memory by the third clock;
- a third video signal processing circuit for performing video signal processing using the third clock;
- a second writing control circuit for controlling writing of data into the second memory by the third clock;
- a second clock switch circuit for generating a sync signal by switching the sync signal generated by the first clock to the second clock;
- a second reading control circuit for controlling reading of data from the second memory by the second clock;
- and
- a second video signal processing circuit for performing video signal processing using the second clock.
A video signal processing apparatus comprising:
- a first clock generation circuit for generating a first clock synchronized with an input signal, using a first reference clock outputted from a clock oscillation circuit;
- a first video signal processing circuit for performing video signal processing using the first clock;
- a second clock generation circuit for generating a second clock according to a resolution of a pixel display;
- a third clock generation circuit for generating a third clock by multiplying a second reference clock outputted from a second clock oscillation circuit by L (L:
- integer);
- a first writing control circuit for controlling writing of data into a first memory by the first clock;
- a first clock switch circuit for generating a sync signal that is switched to the third clock, using the sync signal generated with the first clock;
- a first reading control circuit for controlling reading of data from the first memory by the third clock;
- a third video signal processing circuit for performing video signal processing using the third clock;
- a second writing control circuit for controlling writing of data into the second memory by the third clock;
- a second clock switch circuit for generating a sync signal that is switched to the second clock, using the sync signal generated by the first clock;
- a second reading control circuit for controlling reading of data from the second memory by the second clock;
- and
- a second video signal processing circuit for performing video signal processing using the second clock.
Dependencies are inferred from the claim text.