Dynamic memory clock switching circuit and method for adjusting power consumption

A power reduction circuit for a mobile device wherein the mobile device employs a graphics controller that uses at least a portion of system memory as frame buffer memory, comprising:

• memory controller logic operatively couplable to system memory comprising:
• memory clock control logic operative to:
• first provide a variable memory clock signal to the system memory and to place the system memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal;
• then adjust a frequency of the memory clock signal to a different frequency clock signal;
• and
• in response to the frequency of the memory clock signal becoming stable, restoring the memory to a normal mode that requires the different frequency memory clock signal.

An integrated memory bridge circuit, operatively couplable to system memory, that provides power reduction comprising:

• an integrated graphic controller portion comprising a 3-D rendering engine that uses at least a portion of the system memory as a frame buffer;
• memory controller logic, operatively couplable to the system memory and to the integrated graphics controller, comprising:
• memory clock control logic operative to;
• first provide a variable memory clock signal to the memory and to place the memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal;
• then adjust a frequency of the memory clock signal to a different frequency clock signal;
• and
• in response to the frequency of the memory clock signal becoming stable, restoring the memory to a normal mode that requires the different frequency memory clock signal.

A system that includes power consumption reduction logic comprising:

• system memory;
• a first processor;
• an integrated northbridge circuit that provides power reduction, operatively coupled to the first processor and to the system memory so that the first processor can access the memory, the northbridge circuit comprising:
• an integrated second processor having a portion comprising a 3-D rendering engine that uses at least a portion of the system memory as a frame buffer;
• memory controller logic, operatively couplable to the system memory and to the integrated graphics controller, comprising:
• memory clock control logic operative to;
• first provide a variable memory clock signal to the memory and to place the memory in a self refresh mode wherein the self refresh mode does not require a memory clock signal;
• then adjust a frequency of the memory clock signal to a lower frequency clock signal;
• and
• in response to the frequency of the memory clock signal becoming stable, restoring the memory to a normal mode that requires the lower frequency memory clock signal.