Display driver

A display driver, comprising:

• first to m-th holding circuits (m is an integer greater than or equal to 2) each of which holds and outputs display data of n bits (n is an integer greater than or equal to 2) for at least one pixel;
• a multiplexer that receives display data for a plurality of pixels that is outputted from the first to the m-th holding circuits and time-sharingly outputs the display data for a plurality of pixels in a normal operation mode;
• and
• a D/A converter that, having first to n-th D/A converting input terminals, carries out D/A conversion based on data of n bits that is inputted via the first to the n-th D/A converting input terminals and outputs the output as a gray scale voltage, wherein each of the first to the m-th holding circuits includes first to n-th latch circuits for latching data of each bit of the display data of n bits, the multiplexer includes first to n-th multiplexer output terminals, and, in a test mode for testing the display data, each of the first to the m-th holding circuits serially outputs the display data of n bits that is held in each of the holding circuits as first to m-th serial output data from the output from the n-th latch circuit that is held in each of the holding circuits, with the first to the m-th serial output data being sequentially outputted from the output from the n-th latch circuit of the n-th multiplexer output terminal, the multiplexer outputs the first to the m-th serial output data to the n-th multiplexer output terminal, with the first to the m-th serial output data being sequentially inputted via the n-th multiplexer output terminal to each of the first to the n-th D/A converting input terminals, and the D/A converter carries out D/A conversion every time the data of each bit of the first to the m-th serial output data inputted into the first to the n-th D/A converting input terminals is inputted and outputs the gray scale voltage.

A display driver, comprising:

• first to m-th holding circuits each of which holds and outputs display data for at least one pixel;
• a multiplexer that receives display data for a plurality of pixels that is outputted from the first to the m-th holding circuits and time-sharingly outputs the display data for a plurality of pixels in a normal operation mode;
• a D/A converter that carries out D/A conversion for the display data that is outputted from the multiplexer and outputs the output as a gray scale voltage;
• and
• an output selector in which the gray scale voltage based on the output from the D/A converter is inputted to a first input terminal and which outputs a drive voltage to the drive voltage output terminal,
• wherein each of the first to the m-th holding circuits includes first to n-th (n is an integer greater than or equal to 2) latch circuits for latching data of each bit of the display data for one pixel, and, in the normal operation mode, the multiplexer time-sharingly outputs the display data for a plurality of pixels per pixel and outputs the data of each bit of the display data for each pixel through different wirings, the D/A converter outputs the gray scale voltage based on the display data for one pixel that is outputted from the multiplexer, the output selector outputs the drive voltage from the drive voltage output terminal based on the gray scale voltage that is inputted into the first input terminal, and, in the test mode for testing the display data, each of the first to the m-th holding circuits serially outputs the data latched in the first to the n-th latch circuits from the output from the n-th latch circuit as serial output data while the serial output data that is outputted from each of the first to the m-th holding circuits is inputted into the second input terminal of the output selector via the multiplexer and the output selector outputs voltage based on the data of each bit of the serial output data that is inputted into the second input terminal to the drive voltage output terminal.