Delta-sigma modulator and its application to switching amplification circuit
AssigneeSharp Kabushiki Kaisha
InventorYoshihisa Fujimoto
Life of this patent
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Abstract
A loop delay control circuit is provided between a comparator and a power switch stage. When the amplitude of an input signal is especially high, the loop delay control circuit secures an oscillation threshold value by setting a delay amount at a low value. On the other hand, when the amplitude of the input signal is not so high, the loop delay control circuit reduces an average switching rate by increasing the delay amount, but does not reduce the oscillation threshold value. This makes it possible to provide a delta-sigma modulator allowing realization of both (i) a high oscillation threshold value, i.e., high output power, and (ii) high power efficiency.
Claims14
A delta-sigma modulator, comprising:
- a loop filter;
- a comparator;
- and
- one or more loop delay control circuits, each of which is provided in a loop of the delta-sigma modulator, and each of which controls a loop delay amount by which a signal is delayed,
- each of the loop delay control circuits controlling the loop delay amount in accordance with either (i) a value of the input signal sent to the delta-sigma modulator, or (ii) a value of a signal containing a component of the input signal.
A delta-sigma modulator, comprising:
- a loop filter;
- a comparator;
- and
- a pulse width control circuit, which is provided in a loop of the delta-sigma modulator, and which controls a minimum pulse width of a signal quantized by the comparator,
- the pulse width control circuit controlling the minimum pulse width in accordance with either (i) a value of the input signal sent to the delta-sigma modulator, or (ii) a value of a signal containing a component of the input signal.
Dependencies are inferred from the claim text.