Multi-channel, multi-power class D amplifier with regulated power supply

A power conversion system for Class-D amplification configured to perform envelope-rectification wherein a regulated peak-to-peak voltage maintains a predictable voltage on one or more isolated DC reservoirs without using significant series inductance, and configured to perform active-clamping wherein the regulated peak-to-peak voltage and a constrained high-low duty cycle produces a constantly-running primary switching waveform, the power converter comprising:

• a high frequency isolation transformer, with an air gap core, set to yield a predictable value of shunt inductance, and wherein a first end of the transformer primary winding is coupled to an off-line DC reservoir;
• a first switching transistor configured to couple a second end of the transformer primary winding to a low end of the DC reservoir;
• a second reservoir clamping the primary winding voltage and establishing a “boost voltage,” maintainable at a set voltage by varying an on/off ratio of the first switching transistor;
• a shunt capacitance of sufficient amount, placed across the transformer primary, such that an inductive current stored at the end of each switching period is sufficient to produce a transition to an opposite rail with a predictable, moderate dv/dt in the shunt capacitor to obtain gradual switching transitions without dissipative currents in switching transistors.

A power conversion method comprising:

• coupling a first end of a high frequency isolation transformer primary winding to an off-line DC reservoir;
• sustaining substantial DC current in the primary without saturating, by providing the transformer core with an air gap;
• reducing series inductance;
• ramping up the primary winding current by configuring a first switching transistor to couple a second end of the high frequency isolation transformer primary winding to a low end of the DC reservoir;
• increasing the primary winding voltage to a level higher than the DC reservoir, resembling a boost converter, by turning off the first switching transistor after a predetermined interval;
• establishing a boost-voltage, which is maintained at a set voltage by varying an on/off ratio of the first switching transistor, by clamping the voltage to a second reservoir;
• producing a predictable peak-to-peak voltage by obtaining a desired rectangular on-off waveform constrained between the low side of the DC reservoir and the boost voltage of the second reservoir, as the switching activity continues;
• maintaining predictable voltages on one or more isolated secondary capacitors by rectifying the voltage waveform, which is coupled through transformer windings on the secondary side;
• obtaining relatively gradual switching transitions without dissipative currents in the switching transistors by producing a transition to an opposite rail with a predictable moderate dv/dt in an appropriately sized shunt capacitance across the transformer primary, wherein dv/dt is caused by an inductive current stored at the end of each switching period;
• and
• a configuration wherein:
• a voltage on the boost reservoir is maintained by a controller by using a normal boost-converter control function;
• the second reservoir is loaded by coupling through the high frequency isolation transformer into secondary-side reservoirs, wherein the boost reservoir voltage is coupled to the secondary reservoir voltages and track together.

A Class-D audio power amplifier comprising a full-bridge and a half-bridge operating from a common power supply reservoir, wherein the reservoir is supplied by:

• a high frequency isolation transformer, wherein transformer core is provided with an air gap to sustain substantial DC current in primary winding without saturating and is set to yield a predictable value of shunt inductance, and wherein a first end of the transformer primary winding is coupled to an off-line DC reservoir;
• a first switching transistor configured to couple a second end of the transformer primary winding to a low end of the DC reservoir to ramp up current in the primary winding of the transformer, wherein the first switching transistor is turned off after a certain interval to fly up the primary winding voltage to a level higher than the off-line reservoir, resembling a boost converter;
• a second reservoir clamping the primary winding voltage and establishing a “boost voltage,” maintainable at a set voltage by varying an on/off ratio of the first switching transistor, wherein:
• the rectangular on-off waveform is constrained between the low side voltage of the DC reservoir and the boost voltage of the second reservoir, producing a predictable peak-to-peak voltage;
• the rectangular on-off waveform, coupled through the windings of the transformer, is rectified on the secondary side of the transformer;
• maintaining predictable voltages on one or more isolated secondary capacitors;
• and
• duty cycle of the waveform may be varied, within limits, by a primary-side controller, as required to maintain a specified voltage on the second reservoir against variations of an AC voltage, without affecting the rectified voltage on the secondary side;
• a shunt capacitance of sufficient amount, placed across the transformer primary, such that an inductive current stored at the end of each switching period is sufficient to produce a transition to an opposite rail with a predictable, moderate dv/dt in the shunt capacitor to obtain gradual switching transitions without dissipative currents in switching transistors.

A clocked half-bridge Class-D audio amplification method for a Class-D amplifier, the method comprising:

• synchronizing at least a part of processes by a system clock signal;
• forming a triangular signal by integrating the clock signal;
• pulse-width modulating (PWM) the triangular signal, by a high speed comparator, into a variable duty cycle square signal, using an audio input signal;
• integrating the modulated pulses;
• holding the amplifier in a muting state for a predetermined period wherein switching is disabled;
• raising an output voltage gradually to an operating point during the holding period to avoid large turn-on transient as a result of an average DC voltage appearing abruptly at an onset of switching;
• resuming switching after holding period;
• feeding back a half-bridge output to an amplifier input;
• feeding back from the switched output to the integrator to minimize errors;
• decoupling the average DC voltage of the clock signal;
• decoupling DC content of the output feedback;
• decoupling any DC offset from the audio input section;
• maintaining the average voltage at ground;
• and
• wherein the DC voltage of the comparator input stands substantially at zero, and the PWM signal averages substantially 50% on/off at idle, with excursions from 0 to 100% as driven by the audio input signal, and wherein the substantially 50% idle condition substantially centers the switched waveform between ground and +Vcc, ensuring substantially symmetrical peak output voltages regardless of Vcc voltage.

A clocked full-bridge Class-D audio amplification method for a Class-D amplifier that includes a pair of half-bridge switching sections, the method comprising:

• connecting a load differentially between driven outputs of the pair of half-bridge switching sections;
• synchronizing at least a part of processes by a system clock signal;
• forming a triangular signal by integrating the clock signal;
• pulse-width modulating (PWM) the triangular signal, by a high speed comparator, into a variable duty cycle square signal, with complementary output phases, using an audio input signal;
• integrating the modulated pulses;
• holding the amplifier in a muting state for a predetermined period wherein switching is disabled;
• resuming switching after holding period;
• feeding back a differential signal from the full-bridge output to differential amplifier inputs;
• feeding back a differential signal from the switched output to the integrator to minimize errors;
• decoupling an average DC voltage of the clock signal;
• decoupling DC content of the output feedback;
• decoupling any DC offset from the audio input section;
• maintaining the average differential output voltage substantially at zero by use of a DC servo circuit;
• and
• wherein the DC voltage of the comparator input stands substantially at zero, and the PWM signal averages substantially 50% on/off at idle, with excursions from 0 to 100% as driven by the audio input signal, and wherein the substantially 50% idle condition substantially centers the switched waveform between ground and +Vcc, ensuring substantially symmetrical peak output voltages regardless of exact Vcc voltage, and ensuring substantially zero average differential voltage across the load.