Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of generating a bias reference

A method of generating a bias reference, comprising:

• providing a supply voltage level of at least one transistor threshold voltage plus one transistor saturation voltage;
• generating a reference current from the supply voltage as a function of a feedback voltage;
• mirroring the reference current to a mirrored current generated from the supply voltage;
• generating a first voltage as a function of the mirrored current;
• modifying the feedback voltage in proportion to the first voltage with a cascade feedback buffer configured as a substantially high impedance resistor connected in series with a fourth n-channel transistor, such that the cascade feedback buffer generates the feedback voltage in proportion to the first voltage and wherein the feedback voltage modifies the reference current and the mirrored current to stable values;
• and
• mirroring the reference current to an output current generated from the supply voltage.

A semiconductor device including at least one bias generator, comprising:

• a reference transistor connected in a diode configuration;
• a current sink transistor in a path of the reference transistor configured to generate a reference current;
• a first current mirror configured to generate a mirrored current as a function of the reference current;
• an impedance element in a path of the first current mirror configured to generate a first voltage in proportion to the mirrored current;
• a cascade feedback buffer with an input operably coupled to the first voltage and an output operably coupled to a gate of the current sink transistor, the cascade feedback buffer comprising:
• a substantially high impedance resistor having a first terminal and a second terminal, wherein the first terminal is operably coupled to a supply voltage;
• and
• a buffer current sink comprising an n-channel transistor having a source coupled to a ground voltage, a gate coupled to the input of the cascade feedback buffer, and a drain coupled to the second terminal of the substantially high impedance resistor;
• and
• a second current mirror configured to generate an output current as a function of the reference current.

A semiconductor wafer, comprising;

• at least one semiconductor device including at least one bias generator, comprising:
• a reference transistor connected in a diode configuration;
• a current sink transistor in a path of the reference transistor configured to generate a reference current;
• a first current mirror configured to generate a mirrored current as a function of the reference current;
• an impedance element in a path of the first current mirror configured to generate a first voltage in proportion to the mirrored current;
• a cascade feedback buffer with an input operably coupled to the first voltage and an output operably coupled to a gate of the current sink transistor, the cascade feedback buffer comprising:
• a substantially high impedance resistor having a first terminal and a second terminal, wherein the first terminal is operably coupled to a supply voltage;
• and
• a buffer current sink comprising an n-channel transistor having a source coupled to a ground voltage, a gate coupled to the input of the cascade feedback buffer, and a drain coupled to the second terminal of the substantially high impedance resistor;
• and
• a second current mirror configured to generate an output current as a function of the reference current.

An electronic system, comprising;

• at least one input device;
• at least one output device;
• a processor;
• and
• a memory device comprising, at least one semiconductor memory, including at least one bias generator, comprising:
• a reference transistor connected in a diode configuration;
• a current sink transistor in a path of the reference transistor configured to generate a reference current;
• a first current mirror configured to generate a mirrored current as a function of the reference current;
• an impedance element in a path of the first current mirror configured to generate a first voltage in proportion to the mirrored current;
• a cascade feedback buffer with an input operably coupled to the first voltage and an output operably coupled to a gate of the current sink transistor, the cascade feedback buffer comprising:
• a substantially high impedance resistor having a first terminal and a second terminal, wherein the first terminal is operably coupled to a supply voltage;
• and
• a buffer current sink comprising an n-channel transistor having a source coupled to a ground voltage, a gate coupled to the input of the cascade feedback buffer, and a drain coupled to the second terminal of the substantially high impedance resistor;
• and
• a second current mirror configured to generate an output current as a function of the reference current.