Circuit apparatus and method for operating the same
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorYoshihiro Moriie
Life of this patent
Estimating the term…
Abstract
An LSI includes an operational unit and a switching circuit, and an LSI includes an operational unit and a switching circuit. The operational unit of the LSI generates a switching control signal based on a switching table for supply to the switching circuit. In the switching circuit, each of terminals is connected to any of terminals based on the switching control signal. The operational unit of the LSI generates a switching control signal based on a switching table for supply to the switching circuit. In the switching circuit, each of terminals is connected to any of terminals based on the switching control signal.
Claims21
A circuit device comprising:
- a first semiconductor integrated circuit that has a plurality of first signal pins receiving a plurality of signals, and includes a first circuit performing processing with respect to said plurality of signals;
- and
- a second semiconductor integrated circuit that has a plurality of second signal pins receiving said plurality of signals, and includes a second circuit performing processing with respect to said plurality of signals, wherein
- said plurality of first signal pins and said plurality of second signal pins are interconnected,
- said first semiconductor integrated circuit further includes a first correlation changing unit that changes a correlation between said plurality of signals in said first circuit and said plurality of first signal pins, and
- said first correlation changing unit changes the correlation between said plurality of signals in said first circuit and said plurality of first signal pins on a regular or irregular basis.
(canceled)
(canceled)
A circuit device comprising:
- a first semiconductor integrated circuit that has a plurality of first signal pins receiving a plurality of signals, and includes a first circuit performing processing with respect to said plurality of signals;
- a second semiconductor integrated circuit that has a plurality of second signal pins receiving said plurality of signals, and includes a second circuit performing processing with respect to said plurality of signals;
- and
- a third semiconductor integrated circuit that transmits alteration information via a signal line, wherein
- said plurality of first signal pins and said plurality of second signal pins are interconnected,
- said first semiconductor integrated circuit further includes a first correlation changing unit that changes a correlation between said plurality of signals in said first circuit and said plurality of first signal pins,
- said first correlation changing unit changes the correlation between said plurality of signals in said first circuit and said plurality of first signal pins based on said alteration information transmitted by said third semiconductor integrated circuit, and
- said third semiconductor integrated circuit performs an authentication operation based on voltage on said signal line before transmitting said alteration information.
(canceled)
(canceled)
A circuit device comprising:
- a first semiconductor integrated circuit that has a plurality of first signal pins receiving a plurality of signals, and includes a first circuit performing processing with respect to said plurality of signals;
- and
- a second semiconductor integrated circuit that has a plurality of second signal pins receiving said plurality of signals, and includes a second circuit performing processing with respect to said plurality of signals, wherein
- said plurality of first signal pins and said plurality of second signal pins are interconnected,
- said first semiconductor integrated circuit further includes a first correlation changing unit that changes a correlation between said plurality of signals in said first circuit and said plurality of first signal pins, and
- said first correlation changing unit decrypts alteration information that has been encrypted in advance, to change the correlation between said plurality of first signals in said first circuit and said plurality of first signal pins based on the decrypted alteration information.
(canceled)
(canceled)
(canceled)
A circuit device comprising:
- a first semiconductor integrated circuit that has a plurality of first signal pins receiving a plurality of signals, and includes a first circuit performing processing with respect to said plurality of signals;
- a second semiconductor integrated circuit that has a plurality of second signal pins receiving said plurality of signals, and includes a second circuit performing processing with respect to said plurality of signals;
- and
- a third semiconductor integrated circuit that transmits alteration information, wherein
- said plurality of first signal pins and said plurality of second signal pins are interconnected,
- said first semiconductor integrated circuit further includes a first correlation changing unit that changes a correlation between said plurality of signals in said first circuit and said plurality of first signal pins,
- said second semiconductor integrated circuit further includes a second correlation changing unit that changes a correlation between said plurality of signals in said second circuit and said plurality of second signal pins,
- said first correlation changing unit changes the correlation between said plurality of signals in said first circuit and said plurality of first signal pins based on said alteration information transmitted by said third semiconductor integrated circuit, and
- said second correlation changing unit changes the correlation between said plurality of signals in said second circuit and said plurality of second signal pins based on said alteration information transmitted by said third semiconductor integrated circuit.
A circuit device comprising:
- a first semiconductor integrated circuit that has a plurality of first signal pins receiving a plurality of signals, and includes a first circuit performing processing with respect to said plurality of signals;
- and
- a second semiconductor integrated circuit that has a plurality of second signal pins receiving said plurality of signals, and includes a second circuit performing processing with respect to said plurality of signals, wherein
- said plurality of first signal pins and said plurality of second signal pins are interconnected,
- said first semiconductor integrated circuit further includes a first correlation changing unit that changes a correlation between said plurality of signals in said first circuit and said plurality of first signal pins,
- said first correlation changing unit changes the correlation between said plurality of signals in said first circuit and said plurality of first signal pins based on alteration information,
- said second semiconductor integrated circuit further includes a second correlation changing unit that changes a correlation between said plurality of signals in said second circuit and said plurality of second signal pins,
- said first semiconductor integrated circuit transmits said alteration information to said second semiconductor integrated circuit, and
- said second correlation changing unit changes the correlation between said plurality of signals in said second circuit and said plurality of second signal pins based on said alteration information transmitted by said first semiconductor integrated circuit.
An operation method for a circuit device comprising first and second interconnected semiconductor integrated circuits, comprising the steps of:
- transmitting a plurality of signals between a plurality of first signal pins and a first circuit in said first semiconductor integrated circuit;
- transmitting said plurality of signals between a plurality of second signal pins and a second circuit in said second semiconductor integrated circuit;
- transmitting said plurality of signals between said plurality of first signal pins and said plurality of second signal pins;
- and
- changing a correlation between said plurality of signals in said first circuit and said plurality of first signal pins on a regular or irregular basis.
Dependencies are inferred from the claim text.