Level shifter circuit and semiconductor memory device using same

A semiconductor memory device which includes a memory cell array with memory cells arranged in a matrix and a row decoder circuit selecting a word line of said memory cell array and transferring a voltage to the word line, wherein

• said row decoder circuit includes a level shifter circuit which generates an output voltage according to input of an input voltage and switches an amount of said output voltage by switching a power supply voltage of said output voltage,
• said level shifter circuit comprising:
• a first output MIS transistor of a first conductivity having a first threshold voltage, wherein said output voltage is positively fed back to a gate terminal and said power supply voltage is applied to a first terminal to generate a first voltage at a second terminal;
• a second output MIS transistor of a second conductivity type opposite to said first conductivity type having a second threshold voltage, wherein said first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate said output voltage at a second terminal;
• a first charge MIS transistor connected between the first terminal and gate terminal of said second output MIS transistor, said first charge MIS transistor having a third threshold voltage of the same sign as said first threshold voltage, and upon said input voltage being in a first state, becoming conductive to transfer the voltage of the first terminal of said second output MIS transistor to the gate terminal to keep said second output MIS transistor non-conductive, and upon said input voltage being in a second state, charging a potential of the gate terminal of said second output MIS transistor to a potential defined by an absolute value of said third threshold voltage and switching to a non-conductive state;
• a second charge MIS transistor connected between the first terminal and gate terminal of said second output MIS transistor, said second charge MIS transistor having a fourth threshold voltage of opposite sign to said first threshold voltage, and upon said first voltage being higher than said second voltage by said fourth threshold voltage, becoming conductive to charge the gate terminal of said second output MIS transistor;
• and
• a discharge MIS transistor connected between the first terminal and gate terminal of said second output MIS transistor, said discharge MIS transistor having a fifth threshold voltage of which an absolute value is smaller than said fourth threshold voltage, and upon said first voltage being lower than said second voltage by said fifth threshold voltage, becoming conductive to discharge a charge of the gate terminal of said second output MIS transistor.