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US 2006/0186936 A1Published application
Delay circuitry and method therefor
AssigneeFreescale Semiconductor, Inc.
InventorLipeng Cao
Life of this patent
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Abstract
One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal power and frequency metrics of integrated circuit (29) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.
Claims20
A delay circuit comprising:
- a first delay portion for receiving an input signal and delaying the input signal by a first predetermined amount, the first delay portion comprising a first plurality of same-type logic gates within the first plurality comprising transistors for delaying the input signal, the transistors of the first plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length;
- and
- a second delay portion coupled in series with the first delay portion for delaying the input signal by a second predetermined amount in addition to the first predetermined amount, the second delay portion comprising a second plurality of same-type logic gates within the second plurality comprising transistors for delaying the input signal, the transistors of the second plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length, at least one of transistor threshold voltage, transistor gate length and type of logic gate differing between the first delay portion and the second delay portion.
A method of delaying an input signal comprising:
- receiving an input signal and delaying the input signal by a first predetermined amount by using a first plurality of same-type logic gates comprising transistors;
- forming the transistors of the first plurality of logic gates to each have a substantially same first threshold voltage and a substantially same first transistor gate length;
- coupling a second delay portion in series with the first delay portion for delaying the input signal by an additional second predetermined amount, the second delay portion comprising a second plurality of same-type logic gates comprising transistors;
- and
- forming the transistors of the second plurality of same-type logic gates to each have a substantially same second threshold voltage and a substantially same second transistor gate length, at least one of logic gate type, transistor threshold voltage and transistor gate length differing between the transistors of the first plurality and the transistors of the second plurality.
2 more elements
A method of delaying an input signal comprising:
- receiving the input signal;
- delaying the input signal by a first predetermined amount by using a first plurality of transistors forming logic gates used as delay elements and having a same logic function, each of the first plurality of transistors having a substantially equal first threshold voltage and first gate length;
- and
- subsequently delaying the input signal by a second predetermined amount by using a second plurality of transistors, each of the second plurality of transistors forming logic gates used as delay elements and having a same second logic function, each of the second plurality of transistors having a substantially equal second threshold voltage and second gate length, wherein at least one of the first logic function, the first threshold voltage and the first gate length correspondingly differs from at least one of the second logic function, the second threshold voltage and the second gate length.
1 more element
Dependencies are inferred from the claim text.