Liquid crystal display and test method thereof

A liquid crystal display comprising:

• a plurality of pixel electrodes arranged in a matrix, each pixel electrode having first and second sub-pixel electrodes differentiated in size from each other;
• first and second switching elements connected to the first and second sub-pixel electrodes, respectively;
• first and second gate lines connected to the first and second switching elements, respectively;
• a data line connected to the first and second switching elements and transmitting a data voltage;
• first and second gate shorting bars connected to the first and second gate lines at odd-numbered pixel rows;
• and
• third and fourth gate shorting bars connected to the first and second gate lines at even-numbered pixel rows.

A method of testing a liquid crystal display including a plurality of pixel electrodes having first and second sub-pixel electrodes, first and second switching elements connected to the first and second sub-pixel electrodes, respectively, first and second gate lines connected to the first and second switching elements, respectively, and a data line connected to the first and second switching elements, the method comprising:

• providing first and second gate shorting bars connected to the first and second gate lines, respectively;
• providing a data shorting bar connected to the data line;
• applying a positive data voltage to the data shorting bar;
• applying a first gate test signal to the first gate shorting bar to apply the positive data voltage to the first sub-pixel electrode;
• applying a negative data voltage to the data shorting bar;
• and
• applying a second gate test signal to the second gate shorting bar to apply the negative data voltage to the second sub-pixel electrode.

A method of testing a liquid crystal display including a plurality of pixel electrodes having first and second sub-pixel electrodes, first and second switching elements connected to the first and second sub-pixel electrodes, respectively, first and second gate lines connected to the first and second switching elements, respectively, and a data line connected to the first and second switching elements, the method comprising:

• providing first and second gate shorting bars connected to the first and second gate lines at odd-numbered pixel rows, respectively;
• providing third and fourth gate shorting bars connected to the first and second gate lines at even-numbered pixel rows, respectively;
• providing a data shorting bar connected to the data line;
• applying a positive data voltage to the data shorting bar;
• applying a first gate test signal to the first gate shorting bar to apply the positive data voltage to the first sub-pixel electrode at the odd-numbered pixel rows;
• applying a negative data voltage to the data shorting bar;
• applying second and third gate test signals to the second and third gate shorting bars to apply the negative data voltage to the second sub-pixel electrode at the odd-numbered pixel rows and to the first sub-pixel electrode at the even-numbered pixel rows;
• and
• applying a fourth gate test signal to the fourth gate shorting bar to apply the positive data voltage to the second sub-pixel electrode at the even-numbered pixel rows.

A liquid crystal display comprising:

• a plurality of pixel electrodes arranged in a matrix, each pixel electrode having first and second sub-pixel electrodes differentiated in size from each other;
• first and second switching elements connected to the first and second sub-pixel electrodes, respectively;
• a gate line connected to the first and second switching elements;
• first and second data lines crossing the gate line and connected to the first and second switching elements, respectively;
• and
• first and second data shorting bars connected to the first and second data lines, respectively.

A method of testing a liquid crystal display including a plurality of pixel electrodes having first and second sub-pixel electrodes, first and second switching elements connected to the first and second sub-pixel electrodes, respectively, a gate line connected to the first and second switching elements, and first and second data lines connected to the first and second switching elements, respectively, the method comprising:

• providing first and second data shorting bars connected to the first and second data lines;
• providing a gate shorting bar connected to the gate line;
• applying a positive data voltage to the first data shorting bar;
• applying a negative data voltage to the second data shorting bar;
• and
• applying a gate test signal to the gate shorting bar to apply the positive data voltage to the first sub-pixel electrode and to apply the negative data voltage to the second sub-pixel electrode.