Method and apparatus for semiconductor testing utilizing dies with integrated circuit

A system in which a semiconductor wafer is electrically tested, comprising:

• a semiconductor wafer having multiple dies, each of which has a plurality of contact areas including one or more certain contact areas which are not utilized in the electrical testing, wherein each die comprises a circuit which electrically connects at least one of said certain contact areas to voltage of predetermined magnitude upon receipt by the die of a predetermined signal;
• a probe card having a plurality of probes which contact respective contact areas of a plurality of dies on the wafer but do not contact on each die at least one of said certain contact areas which are connected to voltage of predetermined magnitude;
• and
• an electrical tester connected to said probe card for sending test signals to said probe card and receiving signals therefrom.

A system for electrically testing a semiconductor wafer containing multiple dies, each of which has a plurality of contact areas including two certain contact areas which are not utilized in the testing and are required to be connected to voltage of predetermined magnitude during the testing, comprising:

• a probe card having a plurality of probes which contact respective contact areas of said dies, but do not contact said two certain contact areas;
• an electrical tester connected to said probe card for sending signals to said probe card and receiving signals therefrom;
• and
• a circuit which electrically connects said two contact areas which are not utilized in the testing to a voltage of predetermined magnitude.

A system for electrically testing a semiconductor wafer which enhances the number of channels available for testing, comprising:

• a semiconductor wafer having multiple dies, each of which has a plurality of contact areas including a plurality of certain contact areas which are not utilized in the testing and are required to be connected to reference voltage during the testing;
• a probe card having a plurality of probes which contact respective contact areas on a plurality of dies, but do not contact said plurality of certain contact areas, wherein each probe corresponds to a testing channel;
• and
• an electrical tester for sending testing signals to said probe card and receiving signals therefrom;
• wherein each die of said semiconductor wafer comprises an integrated circuit including a switch and voltage divider which electrically connects each of said plurality of certain contact areas to a reference voltage during said testing, whereby connection of said certain contact areas to reference voltage through said probe card is obviated, thus enhancing the number of probes and corresponding testing channels which can be utilized for testing.

A system in which a static dynamic random access memory (SDRAM) semiconductor wafer of the double data rate (DDR) type is electrically tested, comprising:

• a semiconductor wafer having multiple SDRAM dies of the DDR type, each of which has a plurality of pads, including BCLK and VREF pads which are not utilized in the electrical testing but which are required to be connected to a common reference voltage of predetermined magnitude during the testing, wherein each die also includes a BIST pad and comprises an integrated circuit which electrically connects the BCLK and VREF pads to said voltage of predetermined magnitude upon the BIST pad being connected to ground potential;
• a probe card having a plurality of probes which contact respective pads of one or more dies on the wafer but do not contact on each die said BLCK and VREF pads;
• and
• an electrical tester connected to said probe card for sending test signals to said probe card and receiving signals therefrom.