Methods of fabricating scalable two transistor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorSeung-Jae Baik
Life of this patent
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Abstract
A memory device includes a semiconductor substrate, a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the layer tunnel junction barrier. The device further includes a second gate insulator layer on a sidewall of the tunnel junction barrier, a third gate insulator on a second portion of the substrate adjacent the tunnel junction barrier and a gate electrode on the second gate insulator and the third gate insulator. First and second impurity-doped regions are disposed in the substrate and are coupled by a channel through the first and second portions of the substrate. Fabrication of such a device is also describes.
Claims18
A method of forming a memory device, the method comprising:
- forming a multiple layer pattern including a first gate insulator on a first portion of a semiconductor substrate, a storage node on the first gate insulator, a tunnel junction barrier on the storage node and a data electrode on the tunnel junction barrier;
- forming a second gate insulator layer on a sidewall of the tunnel junction barrier and a third gate insulator on a second portion of the substrate adjacent the multiple layer pattern;
- forming a gate electrode on the second and third gate insulators;
- and
- forming first and second impurity-doped regions in the substrate coupled by a channel through the first and second portions of the substrate.
Dependencies are inferred from the claim text.