US 2006/0186548 A1 · Method of manufacturing semiconductor device and semiconductor device

Abstract

The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film. The second-mask forming layer is etched through the fourth mask to thereby form a second mask having the interconnect trench pattern, and the first insulating film that remains under the bottoms of the via holes is removed. Subsequently, the second insulating film is etched through the second mask to thereby form an interconnect trench, and then the second mask is removed.

A method of manufacturing a semiconductor device having an insulating film that includes a low dielectric constant (low-k) material film having a dielectric constant smaller than a dielectric constant of silicon dioxide, the method comprising the steps of:

(a) sequentially forming a first insulating film and a second insulating film over a substrate that includes a conductive layer pattern in a region including a front surface of the substrate, the first insulating film serving as an interlayer insulating film between interconnect layers and being composed of a low-k material, the second insulating film serving as an insulating film among interconnects and being composed of a low-k material different from the material of the first insulating film;
(b) sequentially forming a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer over said second insulating film, the first-mask forming layer being composed of a low-k material different from the material of the second insulating film, the second-mask forming layer being composed of an insulating material different from the material of the first-mask forming layer, the third-mask forming layer being composed of an insulating material different from the material of the second-mask forming layer, the fourth-mask forming layer being composed of an insulating material different from the third-mask forming layer;
(c) patterning said fourth-mask forming layer to thereby form a fourth mask having an interconnect trench pattern;
(d) forming a resist mask having a via hole pattern on said fourth mask and said third-mask forming layer;
(e) with use of said resist mask as an etching mask, etching said fourth mask, said third-mask forming layer, said second-mask forming layer, and said first-mask forming layer and etching said second insulating film, to thereby open a via hole;
(f) with use of said fourth mask as an etching mask, etching said third-mask forming layer to thereby form a third mask having the interconnect trench pattern, and etching said first insulating film to an intermediate thickness of said first insulating film to thereby extend said via hole downward;
(g) with use of said fourth mask and said third mask as an etching mask, etching said second-mask forming layer to thereby form a second mask having the interconnect trench pattern, and etching said first insulating film that remains under the bottom of said via hole to thereby extend said via hole downward so that said via hole reaches said substrate, said fourth mask being removed as a result of the etching of said second-mask forming layer;
(h) etching said first-mask forming layer with use of said third mask as an etching mask, to thereby form a first mask having the interconnect trench pattern;
(i) after removal of said third mask, forming an interconnect trench in said second insulating film with use of said second mask as an etching mask;
and
(j) removing said second mask after the forming of the interconnect trench.

8 more elements

Facts

Application

11/346,890Filed 3 Feb 2006

Priority

JP 2005-03541414 Feb 2005

Published

24 Aug 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 20/47
Characterised by their insulating parts: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
H10W 20/031
Manufacture or treatment: of conductive parts of the interconnections
H10W 20/071
Manufacture or treatment: of dielectric parts thereof
H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…

Method of manufacturing semiconductor device and semiconductor device

Life of this patent

Method of manufacturing semiconductor device and semiconductor device

Life of this patent

Abstract

Claims11