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US 2006/0186537 A1Published application
Delamination reduction between vias and conductive pads
AssigneeIntel Corporation
InventorsHideki Goto, Toshimi Kohmura
Life of this patent
Estimating the term…
Abstract
Vias and conductive pads configured and coupled in a manner to reduce delamination are described herein. The via and the conductive pads may be located in a substrate such as a carrier substrate, a die, or a printed circuit board.
Claims23
A substrate, comprising:
- a dielectric layer including a dielectric surface;
- a conductive pad on the dielectric surface, the conductive pad having a first and a second surface, the first surface being parallel with the dielectric surface, the second surface intersecting the first surface;
- and
- a via in contact with the first surface and at least a portion of the second surface.
1 more element
A substrate, comprising:
- a dielectric layer, the dielectric layer having a dielectric surface;
- a conductive pad on the dielectric layer, the conductive pad having a first and a second conductive pad surface, the first conductive pad surface being substantially parallel to the dielectric surface and the second conductive pad surface intersecting the first surface;
- and
- a via in contact with at least a portion of the second conductive pad surface to reduce delamination between the via and the conductive pad.
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A method, comprising:
- providing a substrate, the substrate includes a dielectric layer with a dielectric surface;
- forming a conductive pad on the dielectric surface, the conductive pad comprising a first and a second surface, the first surface being substantially parallel with the dielectric surface, the second surface intersecting the first surface;
- and
- forming a via in contact with the first surface and at least a portion of the second surface.
1 more element
A system, comprising:
- a substrate, including:
- a dielectric layer including a dielectric surface;
- a conductive pad on the dielectric surface, the conductive pad having a first and a second surface, the first surface being parallel with the dielectric surface, the second surface intersecting the first surface;
- and
- a via in contact with the first surface and at least a portion of the second surface to reduce delamination between the via and the at least the portion of the second surface;
- an interconnection coupled to the substrate;
- and
- a mass storage coupled to the interconnection.
5 more elements
Dependencies are inferred from the claim text.