Package structure with chip embedded in substrate
AssigneePhoenix Precision Technology Corporation
InventorShih-Ping Hsu
Life of this patent
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Abstract
A package structure with chip embedded in substrate includes: a carrier having a stepped cavity; a semiconductor chip (or a chip set) received in the cavity of the carrier; a dielectric layer formed on the semiconductor chip and the carrier and filled in a gap between the semiconductor chip and the cavity of the carrier to fix the semiconductor chip in the carrier; and a circuit layer formed on the dielectric layer, and electrically connected to electrode pads of the semiconductor chip via a plurality of conductive structures so as to provide external electrical extension for the semiconductor chip via the circuit layer.
Claims12
A package structure with chip embedded in substrate, comprising:
- a carrier having at least one stepped cavity;
- a semiconductor chip received in the stepped cavity, and formed with a plurality of electrode pads thereon;
- a dielectric layer formed on the semiconductor chip and the carrier, and filled in a gap between the semiconductor chip and the carrier, wherein the dielectric layer is formed with conductive structures therein;
- and
- a circuit layer formed on the dielectric layer, and electrically connected to the electrode pads of the semiconductor chip by the conductive structures in the dielectric layer.
A package structure with chip embedded in substrate, comprising:
- a carrier comprising a first carrier layer, a second carrier layer and a third carrier layer, wherein the second carrier layer is mounted on the first carrier layer and has at least one through opening, and the third carrier layer is formed with at least one through opening at a position corresponding to the opening of the second carrier layer, the opening of the third carrier layer being larger in size than the opening of the second carrier layer, so as to form a stepped cavity with opening size increased step by step from bottom to top, for exposing a mounting surface of the first carrier layer and mounting surfaces of the second carrier layer via the stepped cavity;
- a plurality of semiconductor chips received in the stepped cavity of the carrier and mounted on the mounting surfaces of the first and second carrier layers, wherein the semiconductor chips are formed with a plurality of electrode pads thereon;
- a dielectric layer formed on the semiconductor chips and the carrier, and filled in gaps between the semiconductor chips and the carrier, wherein the dielectric layer is formed with conductive structures therein;
- and
- a circuit layer formed on the dielectric layer, and electrically connected to the electrode pads of the semiconductor chips by the conductive structures in the dielectric layer.
Dependencies are inferred from the claim text.