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US 2006/0186530 A1Published application
Memory device power distribution in memory assemblies
AssigneeMicron Technology, Inc.
InventorFrankie Roohparvar
Life of this patent
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Abstract
A memory assembly has a memory package with a plurality of interconnect pins having a plurality of first power input pins located on a first side of the memory package, the first power input pins independent of each other. A lead-over-chip leadframe has a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship. A memory chip is coupled to the plurality of leads and has substrate with a memory device fabricated thereon and a plurality of first power input chip bond pads fabricated thereon and coupled to the memory device. Each first power input chip bond pad is further coupled to one of the first power input pins through one of the leads.
Claims19
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins, wherein the plurality of interconnect pins comprises a plurality of first power input pins located on a first side of the memory package, the first power input pins independent of each other;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having two sides and four quadrants;
- a memory device fabricated on the substrate between the two sides;
- and
- a plurality of first power input chip bond pads fabricated on the substrate and coupled to the memory device, wherein each first power input chip bond pad is further coupled to one of the plurality of first power input pins through one of the leads;
- wherein at least one of the first power input chip bond pads is located in each of at least three of the quadrants of the substrate;
- and
- wherein at least one of the first power input chip bond pads is located near a center of each of the two sides of the substrate.
8 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins, wherein the plurality of interconnect pins comprises a plurality of first power input pins located on a first side of the memory package for coupling to a ground potential and a plurality of second power input pins located on a second side of the memory package for coupling to a supply potential, the first power input pins independent of each other and the second power input pins independent of each other;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having four quadrants;
- a memory device fabricated on the substrate;
- a plurality of first power input chip bond pads for receiving the ground potential, the plurality of first power input chip bond pads fabricated on the substrate and coupled to the memory device;
- and
- a plurality of second power input chip bond pads for receiving the supply potential, the plurality of second power input chip bond pads fabricated on the substrate and coupled to the memory device;
- wherein at least two leads are each coupled to at least two first power input chip bond pads located in multiple quadrants of the substrate;
- and
- wherein at least two leads are each coupled to at least two second power input chip bond pads located in multiple quadrants of the substrate.
9 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having a first side and a second side;
- a memory device fabricated on the substrate between the first and second sides;
- and
- a plurality of chip bond pads fabricated on the substrate and coupled to the memory device;
- wherein a first chip bond pad located between the memory device and the first side of the substrate near a center of the first side is shorted to a second chip bond pad located between the memory device and the second side of the substrate near a center of the second side by one of the plurality of leads of the leadframe.
6 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having four quadrants and further having two sides parallel a major axis of the substrate;
- a memory device fabricated on the substrate;
- and
- a plurality of first power input chip bond pads for receiving a first power input, the plurality of first power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device;
- a plurality of second power input chip bond pads for receiving a second power input, the plurality of second power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device;
- wherein at least one of the first power input chip bond pads is located in each of at least three of the quadrants of the substrate;
- wherein at least one of the first power input chip bond pads is located near a center of each of the two sides;
- wherein at least one of the second power input chip bond pads is located in each of at least three of the quadrants of the substrate;
- and
- wherein at least one of the second power input chip bond pads is located near a center of each of the two sides.
11 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having a first side substantially parallel to a major axis of the memory chip and having two ends and a center, a second side substantially parallel to the major axis and having two ends and a center, and four corners, wherein a corner is located at each end of the first and second sides;
- a memory device fabricated on the substrate;
- at least five first power input chip bond pads for coupling the memory device to a supply potential, wherein at least one first power input chip bond pad is located near each of three corners, at least one first power input chip bond pad is located near the center of the first side, and at least one first power input chip bond pad is located near the center of the second side;
- and
- at least five second power input chip bond pads for coupling the memory device to a ground potential, wherein at least one second power input chip bond pad is located near each of three corners, at least one second power input chip bond pad is located near the center of the first side, and at least one second power input chip bond pad is located near the center of the second side.
6 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having four quadrants between two sides, the sides being parallel a major axis of the substrate;
- a memory device fabricated on the substrate;
- a plurality of supply potential power input chip bond pads for receiving a supply potential, the plurality of supply potential power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device;
- and
- a plurality of ground potential power input chip bond pads for receiving a ground potential, the plurality of ground potential power input chip bond pads fabricated on the substrate along each of the two sides and coupled to the memory device;
- wherein at least one of the supply potential power input chip bond pads is located in each of at least three of the quadrants of the substrate and near a center of each of the two sides;
- and
- wherein at least one of the ground potential power input chip bond pads is located in each of at least three of the quadrants of the substrate and near the center of each of the two sides.
9 more elements
A memory assembly, comprising:
- a memory package having a plurality of interconnect pins;
- a lead-over-chip leadframe having a plurality of leads coupled to the plurality of interconnect pins in a one-to-one relationship;
- and
- a memory chip coupled to the plurality of leads, wherein the memory chip comprises:
- a substrate having a first side substantially parallel to a major axis of the memory chip and having two ends and a center, a second side substantially parallel to the major axis and having two ends and a center, and four corners, wherein a corner is located at each end of the first and second sides;
- a memory device fabricated on the substrate;
- a first supply potential power input chip bond pad located near a first corner;
- a second supply potential power input chip bond pad located near the center of the first side;
- a third supply potential power input chip bond pad located near a third corner;
- a fourth supply potential power input chip bond pad located near the center of the second side;
- a fifth supply potential power input chip bond pad located near a fourth corner;
- a first ground potential power input chip bond pad located near the first corner;
- a second ground potential power input chip bond pad located near the center of the first side;
- a third ground potential power input chip bond pad located near a second corner;
- a fourth ground potential power input chip bond pad located near the third corner;
- and
- a fifth ground potential power input chip bond pad located near the center of the second side;
- wherein each power input chip bond pad is coupled to the memory device.
15 more elements
Dependencies are inferred from the claim text.