Semiconductor device
AssigneeRenesas Technology Corp.
InventorsToshio Sasaki, Fujio Ito, Hiromichi Suzuki
Life of this patent
Estimating the term…
Abstract
The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.
Claims51
A semiconductor device comprising:
- a semiconductor chip which has a main surface, a rear surface, and a plurality of electrodes formed on the main surface;
- a plurality of inner leads arranged around the semiconductor chip;
- a plurality of outer leads formed integral with the plurality of inner leads, respectively;
- a plurality of bonding wires which connect the plurality of electrodes and the plurality of inner leads, respectively;
- and
- a resin encapsulated material which encapsulates the semiconductor chip, the plurality of inner leads, and the plurality of bonding wires,
- wherein the portion in which the plurality of inner leads and the plurality of bonding wires are connected are arranged in a zigzag pattern, and
- the portion in which the plurality of inner leads and the plurality of bonding wires are connected is fixed to the substrate encapsulated inside the resin encapsulated material via an adhesive layer.
A semiconductor device comprising:
- a semiconductor chip which has a main surface, a rear surface, and a plurality of electrodes formed on the main surface;
- a plurality of inner leads arranged around the semiconductor chip;
- a plurality of outer leads formed integral with the plurality of inner leads, respectively;
- a plurality of bonding wires which connect the plurality of electrodes and the plurality of inner leads, respectively;
- and
- a resin encapsulated material which encapsulates the semiconductor chip, the plurality of inner leads, and the plurality of bonding wires,
- wherein the portion in which the plurality of inner leads and the plurality of electrodes are connected are arranged in a zigzag pattern, and
- the portion in which the plurality of inner leads and the plurality of bonding wires are connected is fixed to the substrate encapsulated inside the resin encapsulated material via an adhesive layer.
A semiconductor device comprising:
- a first circuit section formed to be including a transistor which has a current passage between the first potential and the second potential;
- a second circuit section formed to be including a transistor which has a current passage between the third potential and the fourth potential;
- a first pad that supplies the first potential to the first circuit section;
- a second pad that supplies the second potential to the first circuit section;
- a third pad that supplies the third potential to the second circuit section;
- a fourth pad that supplies the fourth potential to the second circuit section;
- a chip that contains the first and the second circuit portions;
- and
- a first lead which is arranged between a plurality of inner leads and supplies the first potential to the first circuit section.
A semiconductor device comprising:
- a first circuit section formed to be including a transistor which has a current passage between the first potential and the second potential included;
- a second circuit section formed to be including a transistor which has a current passage between the third potential and the fourth potential;
- a first pad that supplies the first potential to the first circuit section;
- a second pad that supplies the second potential to the first circuit section;
- a third pad that supplies the third potential to the second circuit section;
- a fourth pad that supplies the fourth potential to the second circuit section;
- a first bus-bar arranged along the direction where the first pad and the second pad are arranged, arranged between a plurality of inner leads and the first and second pads, connected to the first pad by a wire, and supplied with the first potential;
- a second bus-bar arranged along the direction where the first pad and the second pad are arranged, arranged between a plurality of inner leads and the first and second pads, connected to the second pad by a wire, and supplied with the second potential;
- a third bus-bar arranged along the direction where the third pad and the fourth pad are arranged, arranged between a plurality of inner leads and the third and fourth pads, connected to the third pad by a wire, and supplied with the third potential;
- and
- a fourth bus-bar arranged along the direction where the third pad and the fourth pad are arranged, arranged between a plurality of inner leads and the third and fourth pads, connected to the fourth pad by a wire, and supplied with the fourth potential.
A semiconductor device comprising:
- a first circuit section formed to be including a transistor which has a current passage between the first potential and the second potential;
- a second circuit section formed to be including a transistor which has a current passage between the third potential and the fourth potential;
- a plurality of inner leads;
- a first pad that supplies the first potential to the first circuit section;
- a second pad that supplies the second potential to the first circuit section;
- a third pad that is connected to the inner lead supplied with the third potential of the plurality of inner leads by a wire and supplies the third potential to the second circuit section;
- a fourth pad that that is connected to the inner lead supplied with the fourth potential of the plurality of inner leads by a wire and supplies the fourth potential to the second circuit section;
- a first ring-form bus-bar going around the outside of a chip containing the first and the second circuit sections and the first and the fourth pads and connected to the first pad and an inner lead supplied with the first potential of the plurality of inner leads by a wire;
- and
- a second ring-form bus-bar going around the outside of the first ring-form bus-bar, connected to the second pad by a wire, and having an inner lead section to which the second potential is supplied.
A semiconductor device, comprising:
- a first and a second pads arranged on a first row along the side of a semiconductor chip;
- a first inner lead of a plurality of inner leads arranged to surround the semiconductor chip, which is connected to the first pad by a first wire;
- a second inner lead of the plurality of inner leads, which is adjacent to the first inner lead and is connected to the second pad by a second wire;
- a third pad located on a second row along the side of the semiconductor chip and between the first pad and the second pad;
- and
- a first bus-bar arranged along the semiconductor chip and between the semiconductor chip and the first and second inner leads;
- wherein the third pad is connected to the first bus-bar by a third wire that passes between the first wire and the second wire.
A semiconductor device, comprising:
- a plurality of inner leads arranged to surround a semiconductor chip;
- a plurality of input/output pads arranged on the first row of the semiconductor chip and connected to the plurality of inner leads by wires;
- a first bus-bar arranged along the direction of the first row and between the semiconductor chip and the plurality of inner leads, and supplied with the first potential;
- a second bus-bar arranged along the direction of the first row and between the semiconductor chip and the plurality of inner leads and supplied with the second potential;
- and
- a plurality of the first and the second power supply pads arranged between each of the plurality of input/output pads and connected to the first and the second bus-bars by wires;
- wherein the input/output pads, the first power supply pad, the input/output pads, the second power supply power are arranged in that order.
A semiconductor device, comprising:
- a first circuit section containing a transistor which has a current passage between the first potential and the second potential;
- a second circuit section containing a transistor which has a current passage between the third potential and the fourth potential and has a step-down circuit;
- a first pad that supplies the first potential to the first circuit section;
- a second pad that supplies the second potential to the first circuit section;
- a first selection pad connected to the step-down circuit by wiring;
- a second selection pad connected to the step-down circuit by wiring;
- a plurality of inner leads arranged so as to surround a semiconductor chip containing the first and the second circuits;
- a first bus-bar arranged between the semiconductor chip and a plurality of inner leads, connected to the first pad by a wire, and supplied with the first potential;
- a second bus-bar arranged between the semiconductor chip and a plurality of inner leads, connected to the second pad by a wire, and supplied with the second potential;
- and
- a third bus-bar arranged between the semiconductor chip and a plurality of inner leads, connected to the third pad by a wire, and supplied with the third potential;
- wherein, when the first selection pad is connected to the first bus-bar by wire-bonding, the step-down circuit steps down the first potential and supplies the third potential to the second circuit, and
- when the second selection pad is connected to the third bus-bar by wire-bonding, the third potential is supplied from the third bus-bar to the second circuit section without through passing the step-down circuit.
A semiconductor device, comprising:
- a first circuit section formed to be including a transistor which has a current passage between the first potential and the second potential;
- a second circuit section formed to be including a transistor which has a current passage between the third potential and the fourth potential;
- a plurality of inner leads;
- a first pad that supplies the first potential to the first circuit section;
- a second pad that supplies the second potential to the first circuit section;
- a third pad that supplies the third potential to the second circuit section;
- a fourth pad that supplies the fourth potential to the second circuit section;
- a first ring-form bus-bar arranged so as to surround the outer circumference of a chip containing the first and the second circuit sections and the first and the fourth pads and connected to the first and the third pads by wires;
- and
- a second ring-form bus-bar arranged so as to surround the outer circumference of a chip containing the first and the second circuit sections and the first and the fourth pads and connected to the second and the fourth pads by wires;
- wherein the first ring-form bus-bar is electrically isolated by providing a notch between the portion where the first pad comes in contact with and the portion where the third pad comes in contact with, and
- the second ring-form bus-bar is electrically isolated by providing a notch between the portion where the second pad comes in contact with and the portion where the fourth pad comes in contact with.
A semiconductor device, comprising:
- a semiconductor chip having a main surface and a rear surface;
- a plurality of inner leads and outer leads;
- and
- a pair of bus-bars arranged along the semiconductor chip;
- wherein the semiconductor chip comprises electrodes formed on the main surface for a first and a second power supply potentials;
- and
- a circuit electrically connected to one bus-bar via the electrode for the first power supply potential, and further electrically connected to the other bus-bar via the electrode for the second power supply potential;
- and
- to each of the pair of bus-bars, the outer lead is coupled, respectively, and the outer leads respectively coupled to the pair of bus-bars are arranged adjacently.
A semiconductor device, comprising:
- a semiconductor chip having a main surface and a rear surface;
- a plurality of inner leads and outer leads;
- and
- a pair of bus-bars arranged along the semiconductor chip;
- wherein the semiconductor chip comprises electrodes formed on the main surface for a first and a second power supply potentials and an electrode for signals;
- and
- a circuit electrically connected to one bus-bar via the electrode for the first power supply potential, and further electrically connected to the other bus-bar via the electrode for the second power supply potential;
- and
- to each of the pair of bus-bars, the outer lead is coupled, respectively, and the outer leads coupled respectively to the pair of bus-bars are arranged on the opposite side with an outer lead electrically connected to the electrode for signals being positioned therebetween.
A semiconductor device, comprising:
- a semiconductor chip having a main surface, a rear surface, and a plurality of electrodes formed on the main surface;
- a plurality of inner leads arranged on the circumference of the semiconductor chip;
- a plurality of outer leads formed integral with the plurality of inner leads, respectively;
- a plurality of bonding wires that connect the plurality of electrodes and the plurality of inner leads, respectively;
- a sheet-form chip mounting section connected to the semiconductor chip;
- and
- tape members that connect each of the head ends of the plurality of inner leads to the chip mounting section;
- wherein the chip mounting section is smaller than the main surface of the semiconductor chip.
A semiconductor device, comprising:
- a semiconductor chip having a main surface, a rear surface, and a plurality of electrodes formed on the main surface;
- a plurality of inner leads arranged on the circumference of the semiconductor chip;
- a plurality of outer leads formed integral with the plurality of inner leads, respectively;
- a plurality of bonding wires that connect the plurality of electrodes and the plurality of inner leads, respectively;
- a sheet-form chip mounting section connected to the semiconductor chip;
- and
- tape members that connect each of the head ends of the plurality of inner leads to the chip mounting section;
- wherein the chip mounting section is larger than the main surface of the semiconductor chip.
A semiconductor device, comprising:
- a semiconductor chip having a main surface and a rear surface;
- a plurality of inner leads and outer leads;
- a pair of bus-bars arranged along the semiconductor chip;
- and
- a resin encapsulated material for encapsulating the semiconductor chip and the plurality of inner leads;
- wherein the outer lead is coupled to the pair of bus-bars, respectively.
Dependencies are inferred from the claim text.