# US 2006/0186487 A1 · PMOS transistor with increased effective channel length in the peripheral region and method of manufacturing the same

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- Number: US 2006/0186487 A1
- Document ID: US20060186487A1
- Status: Published application
- Kind: A1
- Application number: 11/302,055
- Filed: 2005-12-12
- Published: 2006-08-24
- Earliest claimed: 2005-02-23
- Assignees: Hynix Semiconductor Inc.
- Inventors: Jin Lee
- Web page: https://patentgrep.com/patent/US20060186487A1

## CPC

- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In manufacturing a PMOS transistor, a semiconductor substrate having an active region and a field region is formed with a hard mask layer, which covers a center portion of the active region on the substrate in a lengthwise direction of a channel. The hard mask layer exposes the center portion of the active region in a widthwise direction of the channel and covers both edges of the substrate and the field region adjacent to the both edges. The substrate is etched to a predetermined depth using the hard mask layer as an etching barrier. The hard mask layer is then removed. A gate covering the center portion of the active region is formed on the lengthwise direction of the channel. Source and drain regions are formed at both edges of the gate.

## Claims

### Claim 1

A PMOS transistor having a semiconductor substrate having an active region and an field region surrounding the active region, the PMOS transistor comprising:
a channel area running across the active region from a first field area formed on at least a predetermined portion of the field region to a second field area formed on at least another predetermined portion of the field region,
wherein the first and second field areas are formed such that a predetermined depth exists between the surface of the first and second field areas and the rest of the active and field regions of the semiconductor substrate, and
wherein the first field area extends into the active region by a first width, and wherein the second field area extends into the active region by a second width wherein the first and second widths are same or different from each other,
a gate formed on the channel area of the semiconductor substrate.

### Claim 2

A method of manufacturing a PMOS transistor, comprising the steps of:
providing a semiconductor substrate having an active region and a field region having a first field area and a second field area,
wherein a channel area is formed by the first field area, the second field area, and the predetermined portion of the active region between the first and second field areas, and
wherein each of the first and second field areas is capable of being formed to cover a portion of the active region extending from the respective first or second field area;
forming an isolation layer in the field region of the semiconductor substrate;
forming a hard mask layer on each of the first and second field areas;
etching the semiconductor substrate to a predetermined depth by using the hard mask layer as an etching barrier, wherein the predetermined depth exists between the surface of the first and second field areas and the rest of the active and field regions of the semiconductor substrate;
removing the hard mask layer;
forming a gate on the channel area; and
forming source and drain regions at both edges of the gate on a surface of the semiconductor substrate.

### Claim 3 (depends on 2)

The method of claim 2, wherein the step of forming the isolation layer includes the sub-steps of:
forming a pad oxide layer and a pad nitride layer sequentially to expose the field region on the semiconductor substrate;
etching the semiconductor substrate by using the pad nitride layer as an etching barrier, so as to form a trench;
forming a gap-fill oxide layer on the resultant in order to bury the trench;
performing a chemical and mechanical polishing for the gap-fill oxide layer until the pad nitride layer is exposed; and
removing the remaining pad nitride layer and pad oxide layer after the chemical and mechanical polishing.

### Claim 4 (depends on 3)

The method of claim 3, wherein the pad oxide layer has a thickness of 50˜150 Å.

### Claim 5 (depends on 3)

The method of claim 3, wherein the pad nitride layer has a thickness of 500˜700 Å.

### Claim 6 (depends on 3)

The method of claim 3, wherein the trench has a depth of 2000˜3000 Å.

### Claim 7 (depends on 2)

The method of claim 2, wherein the hard mask layer is an oxide layer.

### Claim 8 (depends on 2)

The method of claim 2, wherein the hard mask layer is formed to have a thickness of 50˜100 Å.

### Claim 9 (depends on 2)

The method of claim 2, wherein the predetermined depth is in the range of 400˜600 Å.

### Claim 10 (depends on 2)

The method of claim 2, wherein a gate oxide layer, a doped polysilicon layer, a tungsten silicide layer, and a gate hard mask layer are sequentially formed on the channel area to form the gate.

### Claim 11 (depends on 10)

The method of claim 10, wherein the gate oxide layer has a thickness of 30˜50 Å.

### Claim 12 (depends on 10)

The method of claim 10, wherein the doped polysilicon layer has a thickness of 400˜700 Å.

### Claim 13 (depends on 10)

The method of claim 10, wherein the tungsten silicide has a thickness of 1000˜1500 Å.

### Claim 14 (depends on 10)

The method of claim 10, wherein the gate hard mask layer has a 2000˜2500 Å.

### Claim 15 (depends on 2)

The method of claim 2, wherein the first field area extends into the active region by a first width, and wherein the second field area extends into the active region by a second width wherein the first and second widths are same or different from each other.