NAND-type flash memory devices and fabrication methods thereof

A method of fabricating a memory device comprising:

• introducing a semiconductor substrate having a cell array region and a peripheral circuit region;
• forming a device isolation layer to define cell active regions and a peripheral active region in the semiconductor substrate;
• forming, on the semiconductor substrate having the device isolation layer, word lines that traverse the cell active regions;
• a string selection line and a ground selection line that are on opposite sides of the word lines, respectively;
• and a peripheral gate pattern that traverses the peripheral active region;
• forming a lower interlayer insulating layer on the semiconductor substrate having the string selection line, the word lines, the ground selection line, and the peripheral gate pattern;
• patterning the lower interlayer insulating layer to form bit line contact holes that expose the cell active regions adjacent to the string selection line located on a first side of the word lines, to form a common source line trench that exposes the cell active regions adjacent to the ground selection line located on a second side opposite to the first side of the word lines, and to form a peripheral gate interconnection contact hole and peripheral metal interconnection contact holes that expose the peripheral gate pattern and the peripheral active region, respectively;
• and
• simultaneously forming, in the lower interlayer insulating layer, bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs, which fill the bit line contact holes, the common source line trench, the peripheral gate interconnection contact hole, and the peripheral metal interconnection contact holes, respectively.

A method of fabricating a memory device comprising:

• introducing a semiconductor substrate having a cell array region and a peripheral circuit region;
• forming a device isolation layer to define cell active regions and a peripheral active region in the cell array region and the peripheral circuit region, respectively;
• forming word lines that traverse the cell active regions;
• a string selection line and a ground selection line that are on opposite sides of the word lines, respectively;
• and a peripheral gate pattern that traverses the peripheral active region;
• forming a lower interlayer insulating layer on the semiconductor substrate;
• patterning the lower interlayer insulating layer to form bit line contact holes that expose the cell active regions adjacent to the string selection line located on a first side of the word lines, to form a common source line trench that exposes the cell active regions adjacent to the ground selection line located on a second side opposite to the first side of the word lines, and to form a peripheral gate interconnection contact hole and peripheral metal interconnection contact holes that expose the peripheral gate pattern and the peripheral active region, respectively;
• simultaneously forming, in the lower interlayer insulating layer, bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs, which fill the bit line contact holes, the common source line trench, the peripheral gate interconnection contact hole, and the peripheral metal interconnection contact holes, respectively;
• and
• forming an upper interlayer insulating layer having via holes that expose the bit line contact plugs, the common source line, the peripheral gate interconnection contact plug, and the peripheral metal interconnection contact plugs.