Phase change memory devices employing cell diodes and methods of fabricating the same

A phase change memory device, comprising:

• a semiconductor substrate of a first conductivity type;
• a lower molding layer provided on the semiconductor substrate to have a plurality of parallel lower openings that expose predetermined regions of the semiconductor substrate;
• a plurality of word lines filling the lower openings, the word lines having a second conductivity type different form the first conductivity type and having substantially flat top surfaces;
• an upper molding layer covering the word lines and the lower molding layer, the upper molding layer having a plurality of upper openings that expose predetermined regions of the word lines;
• first semiconductor patterns provided in the upper openings, the first semiconductor patterns having the first conductivity type or the second conductivity type;
• second semiconductor patterns stacked on the first semiconductor patterns and located in the upper openings, the second semiconductor patterns having the first conductivity type;
• and
• a plurality of phase change material patterns disposed over the second semiconductor patterns and electrically connected to the second semiconductor patterns, respectively,
• wherein interfaces between the word lines and first semiconductor patterns have substantially the same height as interfaces between the word lines and the upper molding layer.

A phase change memory device, comprising:

• a semiconductor substrate of a first conductivity type;
• a first molding layer provided on the semiconductor substrate to have a plurality of first parallel openings that expose predetermined regions of the semiconductor substrate;
• a plurality of word lines filling lower regions of the first openings, the word lines having a second conductivity type different from the first conductivity type and having substantially flat top surfaces;
• a plurality of separating walls disposed in upper regions of the first openings to provide a plurality of second openings that expose predetermined regions of the word lines, the separating walls being composed of a second molding layer having an etch selectivity with respect to the first molding layer;
• first semiconductor patterns in the second openings, the first semiconductor patterns having the first conductivity type or the second conductivity type;
• second semiconductor patterns stacked on the first semiconductor patterns and located in the second openings, the second semiconductor patterns having the first conductivity type;
• and
• a plurality of phase change material patterns disposed over the second semiconductor patterns and electrically connected to the second semiconductor patterns respectively,
• wherein interfaces between the word lines and the first semiconductor patterns have substantially the same height as interfaces between the word lines and the separating walls.

A method of fabricating a phase change memory device, comprising:

• forming a plurality of parallel word lines and a word line isolation layer filling a gap region between the world lines on a semiconductor substrate of a first conductivity type, the word lines being formed to have a second conductivity type different from the first conductivity type;
• forming an upper molding layer on the word lines and the word line isolation layer;
• patterning the upper molding layer to form a plurality of upper openings exposing predetermined regions of the word lines;
• sequentially forming first semiconductor patterns and second semiconductor patterns in the upper openings, the first semiconductor patterns being formed to have the first conductivity type or the second conductivity type, and the second semiconductor patterns being formed to have the first conductivity type;
• and
• forming a plurality of phase change material patterns over the second semiconductor patterns respectively, the phase change material patterns being each electrically connected to the second semiconductor patterns.

A method of fabricating a phase change memory device, comprising:

• forming a first molding layer on a semiconductor substrate of a first conductivity type;
• patterning the first molding layer to form first openings exposing predetermined regions of the semiconductor substrate;
• forming a plurality of word lines in lower regions of the first openings, the word lines being formed to have a second conductivity type different from the first conductivity type;
• forming second molding layer patterns filling upper regions of the first openings, the second molding layer patterns being formed of an insulating layer having an etch selectivity with respect to the first molding layer;
• patterning the second molding layer patterns to form separating walls which provide a plurality of second openings that expose predetermined regions of the word lines;
• sequentially forming first semiconductor patterns and second semiconductor patterns in the second openings, the first semiconductor patterns being formed to have the first conductivity type or the second conductivity type and the second semiconductor patterns being formed to have the first conductivity type;
• and
• forming a plurality of phase change material patterns over the second semiconductor patterns, the phase change material patterns being electrically connected to the second semiconductor patterns respectively.