Non-volatile memory and manufacturing method and operating method thereof

A non-volatile memory, comprising:

• a substrate having a device isolation structure thereon for defining an active region;
• a second conductive type first well disposed on the substrate;
• a first conductive type second well disposed in the second conductive type first well;
• a plurality of second conductive type third wells disposed on the first conductive type second well and isolated from each other by the device isolation structure;
• a plurality of memory cell columns arranged to form an array and disposed on the second conductive type third well, wherein each memory cell column having:
• a plurality of serially connected memory cells isolated from each other by first insulating spacers;
• a select unit connected to the outermost memory cell of the serially connected memory cells through a second insulating spacer;
• a first conductive type source region disposed in the substrate just outside the select unit;
• a first conductive type drain region disposed in the substrate on the other side of the serially connected memory cells;
• a plurality of select lines connected to gates of the select units in the same row;
• a plurality of word lines arranged in parallel in the row direction and connected to gates of the memory cells in the same row;
• a plurality of source lines connected to the first conductive type source regions in the same row;
• and
• a plurality of bit lines arranged in parallel in the column direction with each bit line connected to the first conductive type drains in the same column through a conductive plug, wherein each conductive plug penetrates through the junction between the first conductive type drain region and the second conductive type third well so that the first conductive type drain and the second conductive type third well are short-circuited together.

A method of operating a non-volatile memory, in particular, a memory cell array, wherein the memory cell array comprises:

• a substrate having a device isolation structure thereon for defining an active region;
• a second conductive type first well disposed in the substrate;
• a first conductive type second well disposed in the second conductive type first well;
• a plurality of second conductive type third wells disposed on the first conductive type second well and isolated from each other by the device isolation structure;
• a plurality of memory cell columns arranged to form a the memory cell array disposed on the second conductive type third well such that each memory cell column comprises:
• a plurality of memory cells each having at least a charge-trapping layer and the memory cells serially connected together through spacers without any gaps in-between, a select unit connected to the memory cell on one side of the serially connected memory cells, a first conductive type source region disposed in the substrate just outside the select unit, a first conductive type drain region disposed in the substrate on one the other side of the serially connected memory cells;
• a plurality of select lines connected to gates of the select units on the same row;
• a plurality of word lines arranged in parallel in the row direction and connected to gates of the memory cells in the same row respectively;
• a plurality of source lines connected to the first conductive type source regions on the same row;
• a plurality of bit lines arranged in parallel in the column direction and connected to the first conductive type drain regions on the same column through a conductive plug such that the conductive plug penetrate through the junction between the first conductive type drain region and the second conductive type third well so that the first conductive type drain region and the second conductive type third well are short-circuited together, the method comprising the steps of:
• performing an erasing operation by applying a first voltage to the word lines, applying a second voltage to the first conductive type source lines and the second conductive type third well, applying a third voltage to the select line, the first conductive type second well, the second conductive type first well, setting the bit lines to a floating state, wherein the voltage differential between the first voltage and the second voltage is sufficient to make electrons inject into the charge-trapping layer by FN tunneling to erase the memory cell array.

A method of fabricating a non-volatile memory, comprising the steps of:

• providing a substrate having a device isolation structure thereon for defining an active region;
• forming a second conductive type first well in the substrate;
• forming a first conductive type second well on the second conductive type first well;
• forming a plurality of second conductive type third wells on the first conductive type second well, wherein the second conductive type third wells are isolated from each other by the device isolation structure;
• forming a plurality of stacked gate structures on the substrate, wherein each stacked gate structure comprises a first composite layer, a first gate and a cap layer and there is a gap between two adjacent stacked gate structures;
• forming a plurality of insulating spacers on the sidewalls of the stacked gate structures;
• forming a second composite layer over the substrate;
• forming a conductive layer over the substrate;
• removing a portion of the conductive layer to form a plurality of second gates that completely fill the gaps between the stacked gate structures, wherein the second gates and the stacked gate structures together form a memory cell column;
• forming a first conductive type source region and a first conductive type drain region in the substrate on the sides of the memory cell column respectively;
• forming a first inter-layer insulating layer on the substrate;
• forming a source line in the first inter-layer insulating layer, wherein the source line connects with the first conductive type source region;
• forming a second inter-layer insulating layer on the first inter-layer insulating layer;
• forming a conductive plug in the second inter-layer insulating layer, wherein the conductive plug penetrates through the junction between the first conductive type drain region and the second conductive type third well so that the first conductive type drain region and the second conductive type third well are short-circuited together;
• and
• forming a bit line on the second inter-layer insulating layer, wherein the bit line connects with the conductive plug.