Semiconductor memory device having local etch stopper and method of manufacturing the same

A semiconductor memory device comprising:

• a semiconductor substrate in which a cell region and a core and peripheral region are defined;
• isolation layers formed in the semiconductor substrate to define active regions therein;
• a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region;
• source and drain regions formed in the active regions on respective sides of each of the gate electrode structures;
• self-aligned contact pads contacting the source and drain regions in the cell region;
• an insulating interlayer formed on the semiconductor substrate between the self-aligned contact pads;
• etch stoppers formed on the insulating interlayer in the cell region between the self-aligned contact pads and having top surfaces aligned with top surfaces of the self-aligned contact pads;
• and
• top spacers formed on upper sidewalls of the second gate electrode structure.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming an insulating interlayer on a semiconductor substrate having conductive regions;
• forming contact pads in the insulating interlayer so that the contact pads contact the conductive regions;
• removing a predetermined thickness of the insulating interlayer to partially expose sidewalls of the contact pads;
• and
• forming etch stoppers in spaces created by the removal of the predetermined thickness of the insulating interlayer.

A method of manufacturing a semiconductor memory device, the method comprising:

• forming gate electrode structures in a semiconductor substrate in which a cell region and a core and peripheral region are defined and isolation layers are formed to define active regions;
• forming source and drain regions in the active regions on respective sides of each of the gate electrode structures;
• forming an insulating interlayer on the semiconductor substrate over the source and drain regions;
• etching the insulating interlayer to expose source and drain regions in the cell region;
• forming self-aligned contact pads in the insulating interlayer so that the self-aligned contact pads contact the exposed source and drain regions;
• removing a predetermined thickness of the insulating interlayer;
• forming etch stoppers in spaces created by removing the predetermined thickness of the insulating interlayer in the cell region;
• and
• forming top spacers on upper sidewalls of the gate electrode structure in the core and peripheral region.