US 2006/0186459 A1Published application

Non-volatile memory and manufacturing method thereof

AssigneePowerchip Semiconductor Corp.

InventorsKo-Hsing Chang, Chiu-Tsung Huang

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Abstract

A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.

Claims18

Dependent claims

A non-volatile memory, comprising:

a substrate;
an assist gate disposed on the substrate, wherein the bottom portion of the assist gate has a first width and the top portion of the assist gate has a second width, and the first width is greater than the second width;
a gate dielectric layer disposed between the assist gate and the substrate;
a word line disposed on the substrate;
a floating gate disposed on one side of the assist gate and located between the word line and the substrate, wherein the bottom portion of the floating gate has a third width and the top portion of the floating gate has a fourth width, the fourth width is greater than the third width, and the assist gate, the floating gate and the word line together form a memory unit;
a tunneling dielectric layer disposed between the floating gate and the substrate;
an inter-gate dielectric layer disposed between the word line and the floating gate, between the word line and the assist gate and between the assist gate and the floating gate;
and
a source/drain region disposed in the substrate on the respective sides of the memory unit.

6 more elements

A method of fabricating a non-volatile memory, comprising:

providing a substrate having a gate dielectric layer, a first conductive layer and a cap layer sequentially stacked thereon;
patterning the cap layer, the first conductive layer and the gate dielectric layer to form a plurality of assist gate structures such that there is a gap between every pair of adjacent assist structures, wherein the bottom portion of each assist gate structure has a first width and the top portion of each assist gate structure has a second width, and the first width is greater than the second width;
forming a plurality of source/drain regions in the substrate on one side of the respective assist gate structures;
forming a tunneling dielectric layer and a first inter-gate dielectric layer over the substrate;
forming a plurality of second conductive layer within the gaps between every pair of adjacent assist gate structures, wherein the bottom portion of the second conductive layers have a third width and the top portion of the second conductive layers have a fourth width, and the fourth width is greater than the third width;
removing a portion of the cap layer so that the top surface of the cap layers are below the top surface of the second conductive layers to form a plurality of openings between the second conductive layers;
forming a second inter-gate dielectric layer over the substrate;
forming a third conductive layer over the substrate, wherein the third conductive layer completely fills the openings;
and
patterning the third conductive layer and the second conductive layers to form a plurality of word lines and a plurality of floating gates.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/162,035Filed 26 Aug 2005
Priority: TW 9410555524 Feb 2005
Published: 24 Aug 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 16/0491
Using variable threshold transistors, e.g. FAMOS: virtual ground arrays
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
H10D 30/6892
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…