3-Dimensional flash memory device and method of fabricating the same

A method of fabricating a semiconductor device, the method comprising:

• alternately forming silicon layers doped with impurities and oxide layers on a semiconductor substrate;
• patterning the oxide layers and the silicon layers to form an oxide layer pattern and a silicon layer pattern having a contact hole to expose a region of the semiconductor substrate;
• forming a single crystalline silicon layer on a wall of the contact hole;
• forming a charge storing layer on the single crystalline silicon layer;
• forming a gate in the contact hole;
• patterning the oxide layer pattern and the silicon layer pattern to form a trench to expose the semiconductor substrate and the silicon layer pattern, thereby forming a bit line from the silicon layer pattern;
• forming a trench isolation layer to bury the trench;
• and
• forming a source and a drain region in the silicon layer pattern, the source and the drain region being isolated from each other along a vertical direction, a channel region interposed between the source and the drain regions.

A method of fabricating a semiconductor device, the method comprising:

• alternately forming silicon layers doped with impurities and silicon-germanium layers on a semiconductor substrate;
• patterning the silicon-germanium layers and the silicon layers to form a silicon-germanium layer pattern and a silicon layer pattern having a contact hole to expose the semiconductor substrate;
• forming a single crystalline silicon layer on a wall of the contact hole;
• forming a charge storing layer on the single crystalline silicon layer;
• forming a gate in the contact hole;
• patterning the silicon-germanium layer pattern and the silicon layer pattern to form a trench to expose the semiconductor substrate and the silicon layer pattern, thereby forming a bit line;
• removing the silicon-germanium pattern;
• forming a trench isolation layer to bury the trench;
• and
• forming a source region and a drain region vertically isolated from each other, a channel region interposed between the source and the drain regions.

A 3-dimensional flash memory device comprising:

• a gate extending in a substantially vertical direction on a semiconductor substrate;
• a charge storing layer surrounding the gate;
• a semiconductor layer surrounding the charge storing layer;
• channel regions symmetrically disposed on opposite sides of the gate in the semiconductor layer and isolated from one another vertically;
• and
• source/drain regions symmetrically disposed on opposite sides of the gate in the semiconductor layer and isolated from one another vertically by the channel regions interposed between the source/drain regions.

A method of fabricating a 3-dimensional flash memory device, the method comprising:

• alternately forming silicon layers having doped impurities and oxide layers on a semiconductor substrate;
• patterning the oxide layers and the silicon layers to form a trench to expose the semiconductor substrate and to form a bit line from the silicon layer;
• forming a trench isolation layer that buries the trench;
• forming a contact hole to expose the semiconductor substrate by etching the trench isolation layer;
• forming a single crystalline silicon layer on the wall of the contact hole;
• forming a charge storing layer on the single crystalline silicon layer;
• forming a gate in the contact hole;
• and
• forming source/drain regions on both sides of each of the channel regions and forming channel regions isolated from one another in a vertical direction in the silicon layer on both sides of the gate.

A semiconductor device comprising:

• a cylindrical gate that vertically extends from a semiconductor substrate;
• a charge storing layer concentrically surrounding the cylindrical gate;
• a semiconductor layer concentrically surrounding the charge storing layer;
• channel regions disposed in the semiconductor layer;
• and
• source/drain regions disposed in the semiconductor layer and isolated from one another vertically by the channel regions.